Micross

14th International Conference and Exhibition on
DEVICE PACKAGING
www.imaps.org/devicepackaging

WekoPa Resort and Casino
Fountain Hills, Arizona USA

IMAPS Device Packaging

Conference and Technical Workshops
March 6-8, 2018
Exhibition and Technology Showcase
March 6-7, 2018
Professional Development Courses
March 5, 2018
GBC Plenary Session
March 7, 2018
Device Packaging (Amkor Image)
Courtesy of Amkor Technology
Device Packaging (RDEDCOM image)
Courtesy of US Army RDEDCOM AMRDEC

General Chair:
Peter Ramm
Fraunhofer EMFT Munich


General Chair-Elect:
Jon Aday
Qualcomm


Past General Chair:
Rozalia Beica
Dow Electronic Materials

Past General Chair:
Gilles Poupon
CEA




TECHNICAL PROGRAM | FINAL PROGRAM PDF | SPEAKERS | PROFESSIONAL DEVELOPMENT COURSES (PDCs)
EXHIBIT DETAILS (SOLD OUT) | 2018 EXHIBITORS | 2018 Exhibit Floorplan
EXHIBIT/SPONSOR PROSPECTUS | GES EXHIBITOR "KIT"


TECHNICAL PROGRAM

Amkor
Courtesy of Amkor Technology

The Largest 2018 Conference Dedicated to...

Interposers, 3D IC & Packaging;

Fan-Out, Wafer Level Packaging
& Flip Chip;

Engineered Micro Systems/Devices
(including MEMS/Sensors...)

Amkor
Courtesy of Amkor Technology

We hope to see you March 5-8, 2018 for this year’s Device Packaging Conference!
**2017 Conference presentations available at WWW.IMAPSOURCE.ORG**

 

Thank you to our Premier PLATINUM Sponsor:

Thank you to our Premier GOLD Sponsors:

Premier Gold 
Sponsor - EMD Performance Materials
Premier Gold Sponsor - XYZTEC

Thank you to our Premier SILVER Sponsors:

Premier Silver Sponsor: Amkor Technology
Premier Silver Sponsor: NAMICS
Premier Silver Sponsor: Cadence
Premier Silver Sponsor: Mentor Graphics Premier Silver Sponsor: Kyocera

 

2018 Conference Overview:

The 14th Annual Device Packaging Conference (DPC 2018) will be held in Fountain Hills, Arizona, on March 5-8, 2018. It is an international event organized by the International Microelectronics Assembly and Packaging Society (IMAPS).

The conference is a major forum for the exchange of knowledge and provides numerous technical, social and networking opportunities for meeting leading experts in these fields. The conference will attract a diverse group of people within industry and academia. It provides a chance for educational interactions across many different functional groups and experience levels. People who will benefit from this conference include: scientists, process engineers, product engineers, manufacturing engineers, professors, students, business managers, and sales & marketing professionals.

 

 

MONDAY, MARCH 5, 2018 -- Professional Development Courses (PDCs) & Welcome Reception
7:00 am - 7:00 pm
Registration
 
**NEW 2-HOUR PDC FORMAT THIS YEAR**
2-HOUR COURSES - NEW TIMES/SCHEDULE
10:00 am - 12:00 pm
Morning Professional Development Courses (PDCs) - 10am-12pm

(ROOM 102)

PDC1:Stencil Printing Technology for Bumping and Advanced Semiconductor Assembly Applications
COURSE CANCELLED

(ROOM 106)

PDC2: Polymer Challenges in 2.5D and 3D Packaging
Course Leaders: Jeffrey Gotro, InnoCentrix, LLC

(ROOM 105)

PDC3: The Science of Bond Testing
Course Leader: Bob Sykes, XYZTECbv

(ROOM 103)

PDC4: Temporary Bonding of Electronics (Wafers, Packages, Displays)
Course Leader: John Moore, Daetec LLC

(ROOM 104)

PDC5: Introduction to System in Package (SiP) - The Heterogeneous Integration Driver
Course Leader: Mark Gerber, ASE US

12:00 pm - 1:00 pm
LUNCH - Only provided for those attendees registered for both Morning AND Afternoon PDCs
1:00 pm - 3:00 pm
Early Afternoon Professional Development Courses (PDCs) - 1pm-3pm

(ROOM 106)

PDC6: Emerging Challenges in Semiconductor Packaging – Part 1 (Design)
Course Leader: Raja Swaminathan, Intel

(ROOM 105)

PDC7: Fundamentals of 3D and 2.5D Packaging Integration
Course Leaders: Urmi Ray, STATS ChipPAC

(ROOM 103)

PDC8: The Evolution of High Density Packaging
Course Leader: Phil Garrou, Microelectronic Consultants of NC

(ROOM 104)

PDC9: Introduction to Solder Flip Chip with an Emphasis on Cu Pillars
Course Leader: Mark Gerber, ASE US

3:00 pm - 3:30 pm
BREAK
3:30 pm - 5:30 pm
Late Afternoon Professional Development Courses (PDCs) - 3:30pm-5:30pm

(ROOM 106)

PDC10: Emerging Challenges in Semiconductor Packaging – Part 2 (Manufacturing)
Course Leader: Raja Swaminathan, Intel

(ROOM 105)

PDC11: Manufacturing Failure Analysis and Test Strategies for TSV 3D Packages
Course Leaders: Bruce Kim, City University of New York

(ROOM 103)

PDC12: MEMS and nanoMEMS Packaging
Course Leader: Slobodan Petrovic, Oregon Institute of Technology

(ROOM 104)

PDC13: Fan Out Packaging Evolution & Complexity
Course Leader: John Hunt, ASE US

5:30 pm - 7:30 pm

Welcome Reception
(CONFERENCE CENTER FOYER -- All Attendees Are Invited To Attend)

Sponsored by:

Premier Platinum Sponsor: ASE US, Inc.

Premier Gold 
Sponsor - EMD Performance Materials

Premier Gold Sponsor - XYZTEC

Premier Silver Sponsor: Amkor Technology

Premier Silver Sponsor: NAMICS

Premier Silver Sponsor: Cadence

Premier Silver Sponsor: Mentor Graphics

Premier Silver Sponsor: Kyocera

 

 

 

 

TUESDAY, MARCH 6, 2018 -- Morning Keynote Presentations

7:00 am -
7:00 pm

Registration

7:00 am -
8:00 am

Continental Breakfast Sponsored by:

Premier Gold 
Sponsor - EMD Performance Materials Premier Gold Sponsor - XYZTEC


8:00 am -
8:20 am

(ROOM 107-108)

OPENING COMMENTS
General Chair:
Peter Ramm, Fraunhofer EMFT Munich

Keynote Sessions Sponsored by:

SPTS - Corporate Sponsor

8:20 am -
9:05 am

(ROOM 107-108)

KEYNOTE 1:
3D-IC: Past, Present and Future

Though the process flows and technologies required to implement 3DIC were being developed in the late 1980's and early 1990's by pioneers such as Mitsu Koyanagi in Japan and Peter Ramm in Germany, the decade of 3DIC started in earnest in the 2007-2008 timeframe with the commercial announcement by Toshiba of CMOS Image sensor modules with TSV. This was quickly followed by announcements from Samsung, IBM and TSMC indicating that 3DIC was the key technology to future integration and would in some ways be the savior to our industry as scaling, as described by "Moore's Law" slowly came to an end. In this presentation we will take a look at how 3DIC has developed over the decade, where we are and where we are going.

Keynote - Phil Garrou

Phil Garrou, Microelectronic Consultants of NC
Dr. Philip Garrou retired from Dow Chemical in 2004 as Global Director of Technology for their Advanced Electronic Materials business unit. He is now contributing editor and blogger ("Insights from the Leading Edge") for Solid State Technology, a subject matter expert (SME) for DARPA and runs his consulting company Microelectronic Consultants of NC in the RTP area.

9:10 am -
9:55 am

(ROOM 107-108)

KEYNOTE 2:
2D to 3D Package Architectures - Back to the Future

Moore's Law Scaling has driven electronics industry growth and new package architectures (including 3D architectures and architectures currently defined as 2.1D, 2.3D or 2.5D architectures) are projected to be major enablers to maintain the pace of Moore's law scaling and enable heterogeneous integration. Historically, packaging has scaled sufficiently to act as a space and electrical transformer to enable transistor/silicon scaling, and innovations in packaging were focused on minimizing impact to the power, performance and latency of silicon. With an increasing drive for heterogeneous integration, packaging is being increasingly challenged to deliver power-efficient, high bandwidth on/off package low power links and meet diverse functionality ranging from high performance servers to flexible, wearable electronics. This talk will introduce a new IEEE standardized industry nomenclature on package architectures covering and clearly demarcating both 2D and 3D constructions, as well as highlight the key metrics driving the evolution of these architectures, their current values (based on the state of the art) and projections for the next 5-10 years. This is expected to drive focus and direction to industry, academia and government on critical technology trends and motivations for research needed to meet next generation requirements in the 2D-3D architecture space.

Keynote - Raja Swaminathan

Dr. Raja Swaminathan, Package Architect, Intel Corporation
Dr. Raja Swaminathan is an IEEE senior member and is a package architect at Intel for next generation server, client and mobile products. His expertise is on delivering integrated HVM friendly package architectures with optimized electrical, mechanical, thermal solutions. He is an IEEE, ITRS and iNEMI roadmap author on packaging and design. He has also served on IEEE micro-electronics and magnetics technical committees. He has 26 patents and 25 peer-reviewed publications and holds a Ph.D. in Materials Science and Engineering from Carnegie Mellon University.

10:00 am -
6:30 pm

EXHIBITION AND TECHNOLOGY SHOWCASE
(WASAJA BALLROOM

10:00 am -
10:30 am

Break in the Exhibit Hall Sponsored by:

Break Sponsor - Intevac

 

SPTS - Corporate Sponsor

 

 

TUESDAY, MARCH 6, 2017 -- Morning Technical Sessions

Interposers, 3D IC & Packaging

Fan-Out, Wafer Level Packaging & Flip Chip

Engineered Micro Systems/Devices
(including MEMS & Sensors)

TUESDAY MORNING SESSIONS

(ROOM 104-106)

TA1:
APPLICATION - SiP

Chairs: Rama Puligadda, Brewer Science; Diane Scheele, Versum Materials

(ROOM 107-108)

TA2:
FAN-OUT WAFER LEVEL PACKAGING; TECHNOLOGY

Chairs: John Hunt, ASE Group; Rebecca Schmidt, DOW Electronic Materials

(ROOM 102-103)

TA3:
RF & QUANTUM DEVICES

Chairs: Li-Anne Liew, UC Boulder / NIST; and Keaton Rhea, Auburn University

10:30 am - 11:00 am

081
Market and Technology Trends of Advanced Packaging for SiP Application
Santosh Kumar, Yole Developpement

006
Cost and Yield Analysis of RDL Creation in Fan-out Wafer Level Packaging
Amy Lujan, SavanSys Solutions LLC

005
A Wafer-Bonding Method for Fabricating Integrated GaAs Schottky Varactor Multipliers on Silicon Platforms
Robert M. Weikle II, University of Virginia (Linli Xie, Souheil Nadri, Naser Alijabbari, Masoud Jafari, Michael E. Cyberey, N. Scott Barker, Arthur W. Lichtenberger)

11:00 am - 11:30 am

077
Multi-die Connectivity and the Proposition for Heterogeneous IC Packaging
Mike Kelly, Amkor Technology

020
Embedded Wafer Level Ball Grid Array as One Solution for 2.5D System in Package
Jacinta Aman Lim, STATS ChipPAC

022
Quasi-Optical Directional Coupler for Ultra-Wideband THz Vector Network Analyzers
Yiran Cui, Arizona State University (Georgios C. Trichopoulos)

11:30 am - 12:00 pm

014
Improving Solder Joint Reliability in SiPs Using Plasma-Based Nanocoating for Top Coat
Abe Ghanbari, Semblant (Simon McElrea)

028
Moving from Wafer Level Packaging to Panel Format
Moody Dreiza, Atotech Deutschland GmbH (Henning Huebner, Christian Ohde, Ralph Zoberbier, James Welsh)

054
Nonequilibrium Transport in the Pseudospin-1 Dirac-Weyl System
Cheng-Zhen Wang, Arizona State University (Hong-Ya Xu, Liang Huang, and Ying-Cheng Lai)

12:00 pm - 12:30 pm

064
3D Modular Power Electronic Systems, based on Embedded Components
Lars Boettcher, Fraunhofer IZM Berlin (S. Karaszkiewicz , Th. Loeher, D. Manessis , A. Ostmann)

066
Innovative Wafer Fan-out Technologies -- Heterogeneous Integration for a Connected World
Curtis Zwenger, Amkor Technology (WonChul Do, Eoin O'Toole)

050
Out-of-Time-order Correlator in Billiard Systems
Chendi Han, Arizona State University (Hongya Xu, Ying-Cheng Lai)

12:30 pm -
2:00 pm

Lunch In The Exhibit Hall Sponsored by:
(Food served from 12:30 pm - 1:30 pm)

DPC/GBC Premier Sponsor: ASE US, Inc.

 

 

TUESDAY, MARCH 6, 2018 -- Afternoon Technical Sessions, Exhibit Hall Reception & Evening Panel on Advanced Packaging

Interposers, 3D IC & Packaging

Fan-Out, Wafer Level Packaging & Flip Chip

Engineered Micro Systems/Devices
(including MEMS & Sensors)

TUESDAY
AFTERNOON
SESSIONS

(ROOM 104-106)

TP1:
TSV / TGV / 3DIC

Chairs: Lars Böttcher, Fraunhofer IZM; Stevan Hunter, ON Semiconductor

(ROOM 107-108)

TP2:
FAN-OUT WAFER LEVEL PACKAGING; APPLICATIONS

Chairs: Amy Lujan, SavanSys Solutions; Curtis Zwenger, Amkor Technology

(ROOM 102-103)

TP3:
CHAOTIC & NONLINEAR SYSTEMS
Chairs: Ned Corron, US Army AMRDEC; Aubrey Beal, US Army AMRDEC

2:00 pm -
2:30 pm

029
2018 A Turning Point for 3D TSV Integration: will AI be the Real Opportunity for 3D and 2.5D Integration?
Emilie Jolivet, Yole Developpement (Thibault Buisson)

009
Fan-Out Wafer-Level-Packaging: Market and Technology Trends
Jerome Azemar, Yole Developpement

002
Large Class of Optimal Communication Waveforms Exhibit Chaos
Marko Milosavljevic, U. S. Army Aviation & Missile Res., Dev., & Eng. Center (Ned Corron, Jonathan Blakely)

2:30 pm -
3:00 pm

NEW SPEAKER:
Process Development Update of Through Glass Vias and Through Quartz Vias (TQV) for 2.5 and 3D Packaging
Vern Stygar, AGC


SPEAKER CANCELLED ALL HIS TALKS - FEB. 27
3d Die Stacks w/o TSVs that Operate at Comparable High Bandwidth and Power Efficiency
Dev Gupta, APSTL llc

067
Packaging and Integration Strategy for mmWave Products
Urmi Ray, STATS ChipPAC, Inc.

042
Wireless Communication Demonstration in Hardware Using an Exactly Solvable Chaotic System
D. Aaron Whitney, Auburn University (Benjamin K. Rhea, Andrew Muscha, Frank Werner, R. Chase Harrison, Robert Dean)

3:00 pm -
3:30 pm

073
Advantages of through glass via (TGV) for RF Front End
Pramodh Bangaloremadhuranath, Corning Incorporated

044
Packaging and Assembly Challenges for Automotive ADAS
Linda Bal, TechSearch International, Inc (E. Jan Vardaman)

036
Chaos in a Linear Wave Equation
Ned Corron, US Army AMRDEC

3:30 pm -
4:00 pm

Break in Exhibit Hall Sponsored by:

Break Sponsor: 
TechSearch International

4:00 pm -
4:30 pm

NEW SPEAKER:
Reducing Thermal Coupling Using Fluid Cooled Low-K Interposers
Stevan Hunter, Michael Fish, Patrick McCluskey, and Avram Bar-Cohen, University of Maryland, College Park


CANCELLED BY SPEAKER - FEB. 27

Rapid Physical Prototyping of Microelectronic Systems using Heterogeneous Technologies with Silicon Interposers
Gord Harling, Innotime Technologies (Frederick Kalinian)

069
Panel Chip Last Fan-out Warpage Analysis and Control Strategy
Ian Hu, ASE (Pohsien Sung, Meng-Kai Shih, David Tarng, CP Hung, JY On, Dinos Huang)

037
Szilard's Information Engine: Recent Progress and a Chaotic Analog
Aubrey Nathan Beal, U.S. Army AMRDEC (Jonathan N. Blakely)

4:30 pm -
5:00 pm

043
Glass Solutions for Packaging and RF MEMs
Aric Shorey, Corning Incorporated (Jay Zhang)

NEW SPEAKER:
Title TBD
Jan Vardaman, TechSearch International

 

SPEAKER CANCELLED ALL HIS TALKS - FEB. 27
Comparison of Electrical Performance between FO WLP and Flip Chip on Coreless Substrate ( FC - CLS ) Packages
Dev Gupta, APSTL

017
Non-autonomous Chaotic Circuit that Integrates a Variable Forcing Function on to a Single PCB

Benjamin K. Rhea, Auburn University (R. Chase Harrison, Robert Dean)

5:00 pm -
5:30 pm

046
Progress in Time-Domain Optical Coherence Tomography for TSV/3Di stacking Metrology
Dario Alliata, UnitySC (Guillaume Vienne, UnitySC; Charankumar Godavarthi, Eric Legros, Jean-Philippe Piel, Philippe Parbaud, Christian Neel, Fogale Nanotech)

071
Addressing the Challenges of Multi-layer Polymer Processing for Fan-Out Wafer Level Packaging
Ken Sautter, Yield Engineering Systems, Inc.  

051
Stretching Time in FPGAs: Chaos Enhanced Entropy using Asynchronous Logic
Seth Cohen, Southern Research (Ned Corron, US Army AMRDEC)

5:30 pm -
6:30 pm

Exhibit Hall Reception
Sponsored by:

Corporate Sponsor - NGK NTK

Corporate Sponsor - Dow Electronic Materials

Corporate Sponsor - Technic

6:30 pm -
8:00 pm

(ROOM 107-108)

EVENING PANEL DISCUSSION ON:
Advanced Packaging - What's New? What's Missing? What's Next?

Driven by a continuously increasing number of new applications for instance in the field of IoT with integrated sensor and MEMS; different types of 5G connectivity solutions and mobile communication infrastructure; Automotive electronics for engine and transmission, chassis, safety, driver assistance, passenger comfort and infotainment; faster datacenters with more memory for big data; more space for battery and display in next generation mobile phones; next generation imaging and image recognition systems in mobile devices; power electronics; processing cryptocurrency; ... advanced packaging as indispensable part of the final product is facing new challenges in achieving required higher performance, smaller form-factor, higher reliability levels and lower cost. Can existing packaging technologies be extended to meet those requirements? Will large format Panel-Level Packaging bring a cost down? Are new packaging technologies needed? Who will drive and pay the development of those? Will more packaging and test be done by IDMs and Foundries in future instead by OSATs? What is done to get Wafer-Level Chip-Scale Packaging, Fan-Out Wafer-Level Packaging, Heterogenous Integration, System-in-Package and 3D Packaging ready to answer those new challenges? The industry experts in this evening panel discussion will present their view on this and intensively discuss with the audience. Be sure to bring your burning questions about Advanced Packaging - What's new? What's missing? What's next?

MODERATOR:
Urmi Ray, Senior Director, Group Technology Strategy, StatsChipPac

PANELISTS
:
Glenn Daves, Head of Package Innovation, NXP Semiconductors N. V.
Erica Folk, Manager, MMIC/RFIC Design, Northrop Grumman
Markus Leitgeb, Program Manager, R&D, AT&S
Ravi Mahajan, Fellow, Co-Director High Density Interconnect Pathfinding, Intel
Paul Mescher, Principal Packaging Technologist, Microsoft
Susan Trulli, Sr. Engineering Fellow, Raytheon Company

 

Panel Session & Refreshments Sponsored by:
Evening Panel & Reception Sponsor: Yield Engineering Systems, Inc.(YES)

 

 

WEDNESDAY, MARCH 7, 2018 -- GBC Keynote & Plenary Session

7:00 am -
6:00 pm

Registration

7:00 am -
8:00 am

Continental Breakfast Sponsored by:

Premier Gold 
Sponsor - EMD Performance Materials Premier Gold Sponsor - XYZTEC


 

(ROOM 107-108)

GBC
Welcome to the Global Business Council (GBC) Keynote & Plenary Session on
AUTOMOTIVE SYSTEMS DRIVING NEW MICROELECTRONICS OPPORTUNITIES

8:00am - 8:15am

(ROOM 107-108)

OPENING COMMENTS:
GBC Chairs:
Lee Smith, (UTAC) United Test & Assembly Center; Thomas Goodman, Izinus

8:15am - 9:00am

(ROOM 107-108)

GBC KEYNOTE:
PACKAGING AND THE AUTONOMOUS CAR

Autonomously driving cars are the near goal for many ongoing development efforts in the automotive industry. Electronics systems required to accomplish this end continue to evolve. Even so, system architectural and component decisions are becoming clear, including sensing requirements, workload partitioning between centralized and distributed computing nodes, security, and communications. These combine to drive great diversity in the types and capabilities of the microelectronic packaging required to support them. The interplay between self-driving system components and architecture on the one hand and, on the other, the packaging required will be expanded and explored, with relevant examples given.

GBC Keynote - Glenn Daves

Glenn G. Daves, Head of Package Innovation, NXP Semiconductors N. V.
Glenn G. Daves is Vice President of Package Innovation at NXP Semiconductors. He is responsible for package design, technology development, and assembly process development in support of NXP's full product portfolio. NXP serves diverse markets, each diving unique requirements: automotive (where NXP is the #1 supplier in the industry), handheld, consumer, industrial, banking, medical, and military. Prior joining NXP, Glenn led packaging and printed circuit board development for Freescale Semiconductor. Prior to that, he led global packaging product and technology development at the IBM Corporation. He has also held leadership positions in project management, test and burn-in engineering, and assembly manufacturing engineering. Glenn holds twenty-seven U.S. patents and has degrees from Brown University, the University of Illinois at Urbana-Champaign, and Alliance Theological Seminary.

9:00am - 9:30am

Market Drivers and Packages for Automotive Electronics: What's New and What's Not?
Jan Vardaman, TechSearch International
Automobiles are on the threshold of a radical change in technology with the move to autonomous driving. Today's vehicles have increased connectivity, improved self-diagnostics, a greater number of safety features including crash avoidance technology and other advanced driver assistance. Many of the packages adopted for these new automotive features have similar form factors and function to other applications such as smartphones and high performance computing. However, packages for automotive electronics must meet a different set of requirements. How do the packages used in other applications differ from automotive electronics? What is common? This presentation examines the trends in new packages for automotive electronics and compares and contrast packages from other applications. Included are discussion on the packages for sensors, including fan-out wafer level packages (FO-WLP) for radar and flip chip processors for sensor fusion. Will the packages for automotive sensors be able to leverage the technology developments and the economies of scale introduced by the mobile device era? This presentation explores the drivers for automotive packaging and examines the potential use and pitfalls of packaging and assembly technology from mobile devices.

9:30am - 10:00am

MEMS & Sensors for Next Generation Automotive
Santosh Kumar, Yole Developpement
In a global automotive market worth than US$2.3T, the little world of automotive sensors has recently been shaken up by the emergence of electric and autonomous cars. Despite just 3% growth in the volume of cars sold expected through to 2022, Yole Developpement expects an average growth rate in sensors sales volumes above 8% over the next five years, and above 14% growth in sales value. This is thanks to the expanding integration of high value sensing modules like RADAR, imaging and LiDAR. The current automotive sensing market groups MEMS and classic active sensors such as pressure, tire pressure monitoring systems (TPMS), chemical, inertial, magnetic, ultrasonic, imaging, RADAR and LiDAR.

We estimate that this market is worth US$11B in 2016 and is expected to reach US$23B by 2022. This is mainly due to the boom in imaging, RADAR and LiDAR sensors. Imaging sensors were initially mounted for Advanced Driver Assistance System (ADAS) purposes in high-end vehicles, with deep learning image analysis techniques promoting early adoption. It is now a well-established fact that vision-based Autonomous Emergency Braking (AEB) is possible and saves lives. Adoption of forward ADAS cameras will therefore accelerate. Growth of imaging for automotive is also being fueled by the park assist application, and 360° surround view camera volumes are skyrocketing. RADAR sensors, which are often wrongly seen as competitors of imaging and LiDAR sensors, are increasingly adopted in high-end vehicles. They are also diffusing into mid-price cars for blind spot detection and adaptive cruise control, pushing Level 2/3 features as a common experience. Lastly, LiDAR remains the "Holy Grail" for most automotive players, allowing 3D sensing of the environment.

Among classical sensors like pressure, chemical and magnetic sensors, the impact of electric vehicles will remain small in the short term. However, the advent of electrical vehicles will greatly change the amount and the distribution of pressure and magnetic sensors within the car in the longer term. More electric cars will mean fewer pressure sensors and a surge in magnetic sensors for battery monitoring and various positioning and detection of moving pieces.

The automotive world is experiencing one of the fastest-changing eras in its evolution ever. Sensor suppliers are now engaged in a race where they need to be prepared for the golden age of the automotive world. This presentation will focus on the applications, technologies, trends and players associated with automotive sensor market.

10:00 am -
4:00 pm

EXHIBITION AND TECHNOLOGY SHOWCASE

10:00 am - 10:45 am

Break in the Exhibit Hall Sponsored by:

Break Sponsor - Intevac

10:45am - 11:15am

Automotive Packaging: Evolution, Development and Integration
Shaun Bowers, Amkor Technology, Inc.
Two very large market forces are at play in the automotive electronics market, shaping the way integrated circuit (IC) package development is handled in the future. The primary force is the adoption rate of semiconductor/IC devices in automobiles, which is on track to outpace any other consumer products in semiconductor content. The secondary force is the increasing operational requirements for vehicles due to ride- sharing, connected, electrified and autonomous vehicles, which pushes the limits of traditional device function, size reduction and established reliability envelopes. While the adoption rate of semiconductors in automobiles is somewhat predictable, the integration of typically less robust package platforms is placing the industry in uncharted territory from a performance envelope perspective. How semiconductor packaging engineers address automotive applications will blend the traditional trends of smaller, better, faster and cheaper with the relentless pace of integration, new form-factor adoption and reliability. As the automotive industry adopts new package types typically found in less robust applications, industry-accepted testing methodologies are sometimes not a good match to predict the device performance in the automotive environment. Because the testing and analysis requirements for automotive remain intensive and lengthy, there may be a need to adopt new accelerated tests to reduce development cycle time and accelerate new package and device adoption in the automotive space. In this paper, the traditional failure mechanism based development response is explored with the associated challenges for automotive applications development. Furthermore, methods to abate traditional failures in temp- cycling, high temperature storage, high temperature operating life and biased testing are examined along with associated paths forward to meet the needs of the future. New testing methodologies are investigated to challenge existing testing schemes, and the effects on new package adoption. Finally, this paper will compare the historical automotive response to reliability challenges and explore new methods of development and component testing for new device adoption in the future. © 2017, Amkor Technology, Inc. All rights reserved.

11:15am - 11:45am

Package Integration at Chip and System Level for Automotive Electronics
Venky Sundaram, Georgia Tech
Automotive electronics are experiencing unprecedented growth as the autonomous and electric mobility paradigms take hold. The other major application domains driving electronics content in future cars are HD infotainment and 5G connectivity. Additionally, any automotive electronics technology roadmap must place quality, reliability and functional safety as highest priorities. Adding to the complexity of device and packaging technologies for automotive electronics is the emphasis on low cost and high volumes coming from a mature and stable supply chain. This talk will highlight some of the critical future needs and technology gaps in computing, connectivity, sensing and autonomous driving aspects of automotive electronics. As the functional diversity increases in automotive electronics, transistor scaling and innovations are not sufficient and Heterogeneous package integration (HPI) of a diverse set of active and passive components will be necessary. Package integration in the past has focused primarily on chip-level integration by 2.5D and 3D ICs for high bandwidth, and SiP for active and passive integration. Package integration at system level has been minimal, with system integration on board being the primary approach, leading to bulky and low performance systems, in spite of significant performance size gains at the device level. Georgia Tech has been developing package integration technologies at chip and system levels for high bandwidth computing, 5G communications, low power and high power, and autonomous sensing. This talk will present some examples of the latest advances in package integration for automotive electronics at Georgia Tech, in partnership with global industry to enable a fast transition from R&D to commercialization.

11:45am - 12:00pm

GBC Closing Remarks

12:00 pm -
1:30 pm

Lunch in the Exhibit Hall Sponsored by:
(Food served from 12:00 pm - 1:00 pm)

DPC/GBC Premier Sponsor: ASE US, Inc.

 

 

Corporate Sponsor: Evatec

 

WEDNESDAY, MARCH 7, 2018 -- Afternoon Sessions

Interposers, 3D IC & Packaging

Fan-Out, Wafer Level Packaging & Flip Chip

Engineered Micro Systems/Devices
(including MEMS & Sensors)

WEDNESDAY
AFTERNOON
SESSIONS

(ROOM 104-106)

WP1:
3D ARCHITECTURES AND PROCESSES

Chairs: Rahul Jain, Intel; Gilles Poupon

(ROOM 107-108)

WP2:
FAN-OUT WAFER LEVEL PACKAGE ASSEMBLY; EQUIPMENT AND MATERIALS

Chairs: Mark Gerber, ASE US; Jon Aday, Qualcomm

(ROOM 102-103)

WP3:
MEMS & SENSORS
Chairs: Robert Weikle, University of Virginia; Robert Dean, Auburn University

1:30 pm -
2:00 pm

076
3D and Advanced Packaging Trends in Foundry Space
Hamid Eslampour, GlobalFoundries

004
Direct Metal Replenishment - Cost-effective Novel Method of Replenishing Electrolytic Plating Baths
I. Popova, Ancosys GMBH (H. Cox, C. Rueckl, A. Zhang, J. Stahl)

048
Micro Acoustic Metamaterial for Sound Attenuation
Fuxi Zhang, Auburn University (George Flowers, Robert Dean)

2:00 pm -
2:30 pm

074
Wafer Nano Topography and Edge Roll-Off Metrology for 3D Monolithic Integration
Dario Alliata, UnitySC (Carlos Beitia, M. Abdel Sater, L. Brunet, N. Devanciard, V. Balan, C. Euvrard, Y. Exvrayart, C. Laborderie, CEA LETI; S. Godny, J-F. Boulanger, S. Petitgrand, Y. Guillou, G. Fresquet, UnitySC)

011
Underfill Dispensing for Chip-on-wafer
Akira Morita, Nordson Asymtek (WeiWei Gu, Brian Chung)

049
Environmentally Isolating Packaging for MEMS Sensors
Michael Kranz, EngeniusMicro (Michael Whitley, Carl Rudd, EngeniusMicro, Jeff Craven II, Steven Clark, Robert Dean, George Flowers, Mark Adams, Auburn University)

2:30 pm -
3:00 pm

080
Achieving Monolithic SoC Performance with a Lower Cost, Rapidly Upgradeable 2.5D Modular Architecture: Challenges and Opportunities
Brett Sawyer, Pavel Borodulin, Northrop Grumman

033
Flux Apply, Reflow and Clean in a Single Integrated Tool
Gary Hillman, S-Cubed (Daniel Leske AEMTech, Berlin)

057
Low Pressure Ratio Cascaded Joule-Thomson Cryogenic Coolers
Collin Coolidge, University of Colorado (Li-Anne Liew, Ray Radebaugh, Y.C. Lee)

3:00 pm -
4:00 pm

Break in Exhibit Hall Sponsored by:

Break Sponsor: 
S3IP Binghamton University

4:00 pm -
4:30 pm

070
12:1 Aspect Ratio Mid-process TSV Integration and Functional Test Using Advanced Metallization Processes
Christophe Aumont, STMicroelectronics (Gilles Romero, STMicroelectronics; Thierry Mourier, Mathilde Gottardi, Celine Ribiere, Stephane Minoret, Pierre-Emile Philip, CEA-LETI; Gaelle Guittet, Vincent Mevellec, Aveni)

040
Photo Sensitive PI/PBO for Low Temperature Cure
Daisaku Matsukawa, Hitachi Chemical DuPont MicroSystems, Ltd. (Nobuyuki Saito, Satoshi Abe, Atsutaro Yoshizawa, Noriyuki Yamazaki, Tetsuya Enomoto, Takeharu Motobe, Yuhei Okada, Toshihisa Nonaka)

061
Design of Electrostatic Force Assisted, Piezoelectrically Driven Silicon Chip-based Compressor for Micro Vapor Compression Refrigeration Cooling
Li-Anne Liew, University of Colorado at Boulder, and National Institute of Standards and Technology (Ching-Yi Lin, Collin Coolidge, Y.C. Lee)

4:30 pm -
5:00 pm

023
Laser Full Cut Dicing of Thin Si IC Wafers
Jeroen van Borkulo, ASM Pacific Technologies (Paul Verburg, Richard van der Stam)

015
Linear Transport Degas, Pre-Clean, and PVD Processes for RDL Barrier/Seed Formation in Fan-Out Packaging
Paul Werbaneth, Intevac, Inc. (Babak Adibi, Terry Bluck, Chun-Chung Chen, Daniel Gallagher, Vladimir Kudriavstev, Lisa Mandrell, Billy Runstadler, Chris Smith, Jim Sullivan)

047
A PCB Sensor for Improving Loggerhead Sea Turtle Nesting Research
Rebecca Dean, Auburn University (Robert Dean)

5:00 pm -
5:30 pm

abstract soon

068
Canon Manufacturing Solutions for Advanced Heterogeneous Integration and Fan-Out Wafer Level and Panel Level Packaging Processes
Doug Shelton, Canon USA (Tomii Kume, Sanjay Shinde, Takaaki Tsunoda)

060
3D TSV Inductors for Secure IoT
Bruce Kim, City University of New York (Sang Bock Cho)

 

Device Packaging Poster Session

5:30 pm -
6:30 pm

INTERACTIVE POSTER SESSION & HAPPY HOUR
Outside On Patio Overlooking Desert: 5:30 pm - 6:30 pm
(Poster Presenter Setup - 4:00 pm - 5:25 pm)

Poster Session & Happy Hour Sponsored by:

Corporate Sponsor: Evatec
Poster Session Sponsor: SAMTEC
Mobile Station & Poster Session Sponsor: VEECO
 

007
Sputtered Package Encapsulation Process Improvements with the use of Swing Cathode Rotary Magnetrons
Sarah Williams, Sputtering Components, Inc. (Patrick Morse)

008
The Impact of Glass Style and Orientation on the Reliability of SMT Components
Greg Caswell, DfR Solutions (Maxim Serebrini)

012
Effective Method for Wire Bonds Rework using Conductive Epoxy
Catherine Marsan-Loyer, MiQro Innovation Collaboration Center (C2MI) (Thomas Dequivre)

021
Mechanical Properties of Aluminum Bond Pad Structures with Different Thicknesses
Subramani Manoharan, University of Maryland (Carlos Morillo, Stevan Hunter, Patrick McCluskey)

024
The Application of Immersion Tin for QFN Production
Rick Nichols, Atotech Deutschland GmbH (Hubertus Mertens, Sandra Heinemann, Gustavo Ramos)

031
A Novel Temporary Adhesive for Solder Ball Attachment in Fluxless Reflow System
Hsiang Chuan Chen, Shenmao Technology Inc (Ruei-Ying Sheng, Chen-Yi Chen, Chang-Meng Wang)

045
Inkjet Printing Enables New Semiconductor Packaging Technologies
Wouter Brok, Meyer Burger BV (Erik Corduwener)

072
Temporary Bonding and the Challenge of Cleaning Post Debond
Phillip Tyler, Veeco PSP (Laura Mauer)

078
Integration of a Chemically-Amplified Photoresist and an Advanced Packaging Stepper for Advanced Packaging Technologies
Jack Mach, Rudolph Technologies (Keith Best, Roger McCleary, Rudolph Technologies; Rosemary Bell, Joseph Lachowski, Mitsuru Haga, Inho Lee, Regina Cho, Dow Electronic Materials)

***

071 -- also in Session TP2
Addressing the Challenges of Multi-layer Polymer Processing for Fan-Out Wafer Level Packaging
Ken Sautter, Yield Engineering Systems, Inc.

056 -- also in Session THA3
Successful FPGA Obsolescence Form, Fit, and Function Solution Using a MCM and DER™ to Implement Original Logic Design
Erick Spory, Global Circuit Innovations, Inc.

073 -- also in Session TP1
Advantages of through glass via (TGV) for RF Front End
Pramodh Bangaloremadhuranath, Corning Incorporated

004 -- also in Session WP2
Direct Metal Replenishment - Cost-effective Novel Method of Replenishing Electrolytic Plating Baths
I. Popova, Ancosys GMBH (H. Cox, C. Rueckl, A. Zhang, J. Stahl)

006 -- also in Session TA2
Cost and Yield Analysis of RDL Creation in Fan-out Wafer Level Packaging
Amy Lujan, SavanSys Solutions LLC

033 -- also in Session WP2
Flux Apply, Reflow and Clean in a Single Integrated Tool
Gary Hillman, S-Cubed (Daniel Leske AEMTech, Berlin)

Chaotic Maps in FPGA
Seth Cohen, Southern Research (Ned Corron, US Army AMRDEC)

Plasma Polymerization Applications for Advanced Wafer Level Packaging
Abe Ghanbari, Semblant

 

 

 

SPEAKER WITHDREW ALL HIS PRESENTATIONS ON FEB 27
Fast In Situ Thermo Compression Flip Chip Bonding Process Optimized for 3D Die Stacking
Dev Gupta, APSTL llc

(additional abstracts in regular session will also be invited to participate)
In event of inclement weather, the poster session will be held in the foyer of the conference center

6:30 pm -
8:00 pm

2018 3D InCites Awards Ceremony
Hosted by IMAPS

Immediately Following the Poster Session - Outside On Patio Overlooking Desert

 

Established in 2013 to acknowledge excellence in 3D integration technologies, the 3D InCites Awards program has evolved over the years to be a most coveted prize that recognizes technologies, individuals, and companies that have made significant contributions to the advancement of the heterogeneous integration roadmap. Winners are chosen by industry peers through an online voting process.

In 3D InCites' ongoing commitment to STEM education and finding kid-size cures for childhood cancer, proceeds from this year’s event will benefit two charities: the IMAPS Microelectronics Foundation, which exists to support student activities related to the study of microelectronic packaging, interconnect, and assembly; and Phoenix Children's Hospital pediatric oncology programs, the only institution in Arizona conducting Phase I trials, giving pediatric cancer patients access to the latest and most advanced treatments.

Winners will be announced for the following categories:

  • Device of the Year
  • Process of the Year
  • Manufacturer of the Year
  • Startup of the Year
  • Equipment Supplier of the Year
  • Materials Supplier of the Year
  • EDA Provider of the Year
  • Research Institute of the Year
  • Engineer of the Year

 

 

THURSDAY, MARCH 8, 2018 -- Keynote Presentations

7:00 am -
11:30 am

Registration

7:00 am -
8:00 am

Continental Breakfast Sponsored by:

Premier Gold 
Sponsor - EMD Performance Materials Premier Gold Sponsor - XYZTEC


8:00 am -
8:45 am

(ROOM 107-108)

Keynote Sessions Sponsored by:

SPTS - Corporate Sponsor

(ROOM 107-108)

KEYNOTE 3:
The Growth of Heterogeneous Integration and the Importance of Electronic Materials

Keynote - Rozalia Beica

Rozalia Beica, Global Director New Business Development, DOW Electronic Materials
Rozalia Beica is Global New Business Development Director at Dow Electronic Materials, focusing on identifying and developing new technology and business opportunities for advanced packaging and interconnects. Rozalia has 25 years of international working experience across various industries, including industrial, electronics and semiconductors. For 18 years she was involved in the research, applications and strategic marketing of Advanced Packaging and 3D interconnect technologies, with global leading responsibilities at specialty chemicals (Rohm and Haas), equipment (Semitool, Applied Materials and Lam Research) and device manufacturing (Maxim IC). Prior to joining Dow, Rozalia was the CTO of Yole Développement where she led the market research, technology and strategy consulting activities for Advanced Packaging and Semiconductor Manufacturing. Rozalia has a M.Sc in Chemical Engineering from Polytechnic University "Traian Vuia" in Romania, a M.Sc. In Management of Technology from KW University in the U.S. and an Global Executive MBA from Instituto de Empresa Business School in Spain.

8:45 am -
9:30 am

(ROOM 107-108)

*NEW SPEAKER*

KEYNOTE 4:
System Design Transition from PCB to SiP Solutions

Smartphone, Internet of Things (IoT) and other consumer products demand extreme miniaturization, cost reduction, and continuous performance enhancements. Also, computing and networking products continuously need power reduction, minimized latency, and reduced switching noise level requiring innovative new methods for system integration. In contrast to common understanding, the space for electronic components in vehicles is very limited, so reduced electronic components count, and size are a must for the automotive industry as well. These applications and others have created a new era of printed circuit board (PCB) design transformation to system in package (SiP) design methodology. The need for SiP solutions has driven the entire semiconductor, packaging, design chain and supply chain industries to develop advanced technologies that can address the increasing needs for cost reduction, size reduction and performance enhancements for advanced electronic systems. The transition to SiP design requires new thinking, new approaches and solid methodologies for electronic circuit designs, components integration, assembly process and final testing as well as functional verifications. PCB design is based on horizontal component placement with sufficient distance to minimize electromagnetic coupling among passive components, pre-packaged Integrated Circuits, highly capacitive interconnect structures, and relatively easy to modify and enhance circuits. However, SiP designs are primarily based on vertical component placement, bare dice, and low capacitive interconnect structures to reduce power consumption. This presentation will describe the differences in the two approaches and explain the changes that are occurring to accomplish the transition.

 

Mike Devita, Senior Staff Engineer, Amkor Technology
BIO Soon

9:30 am -
9:45 am

Break in the Foyer Sponsored by:

Break Sponsor - Intevac

 

 

THURSDAY, MARCH 8, 2018 -- Morning Sessions

Interposers, 3D IC & Packaging

Fan-Out, Wafer Level Packaging & Flip Chip

Engineered Micro Systems/Devices
(including MEMS & Sensors)

THURSDAY
MORNING
SESSIONS

(ROOM 104-106)

THA1:
DESIGN & SIMULATION

Chairs: Inho Lee, Dow Electronic Materials; Prithwish Chatterjee, Intel Corporation

(ROOM 107-108)

THA2:
FLIP CHIP ASSEMBLY; EQUIPMENT AND MATERIALS

Chairs: Islam Nokibul, STATSChipPAC; Kevin Martin, Atotech

(ROOM 102-103)

THA3:
ENGINEERED MICROSYSTEMS

Chairs: Bruce Kim, City University of New York; Mike Kranz, EngeniusMicro

9:45 am -
10:15 am

019
Heterogeneous Integration: Are your Design Tools and Methodologies up to the Task?

John Park, Cadence Design Systems

013
Lead Free Solder Plating Chemicals for Substrate Bumping
Koji Tatsumi, Mitsubishi Materials Corporation (Daiki Furuyama, Mami Watanabe, Kyoka Susuki, Takuma Katase, Kiyotaka Nakaya, Masayuki Ishikawa)

041
Thermosonic Ball Bonding Recipe Optimization: Comparing Cu and PCC Wire on Two Pad Thicknesses
Michael Hook, University of Waterloo (Michael Mayer, Stevan Hunter)

10:15 am -
10:45 am

016
Design, Characterization and Testing of Large-area and High-density 3D Interconnection by Direct Bond Interconnect
Gill Fountain, Xperi (Liang Wang, Rajesh Katkar, Michael Huynh, KM Bang, Bongsub Lee, Chandrasekhar Mandalapu, Guilian Gao, Thomas Workman, Gabe Guevara, Cyprian Uzoh, Laura Mirkarimi)

018
Advancement of Fine Pitch Interconnect Technology
Nokibul Islam, StatsChipPAC Inc (Kang KeonTaek)

059
An Agricultural IoT Device for Monitoring Environmental Conditions in Hay Bales
Markus Kreitzer, Auburn University (R. Harrison, J. Craven, A. Muscha, R. N. Dean, E. A. Guertal)

10:45 am -11:15 am

055
A System Co-Design Flow for 3D and Fan-out Package Architectures
Narayanan TV, Zuken USA (Tom Whipple)

034
High-throughput Jetting in Micro-device Packaging
Hanzhuang Liang, Nordson Asymtek

079
Instrumentation for Sensing Passive Eye Response due to Head Impact via MEMS IMUs

Brent Bottenfield, Auburn University (Yuan Meng, Mark Adams)

11:15 am -
11:45 am

 

027
High Precision Uniquely Designed De-flux Cleaning Solution for Advanced Packaging
Ajit Dhamdhere, Cactus Materials, Inc. (Ajit Dhamdhere, Wey Lyn Lee, Tofael Ahmed, Joaquin Santallin, Cactus Materials, Inc.; Takuro Jimbo, Suguru Kamikawaji, Kaken-Tech Co Ltd; Rafiqul Islam, Arizona State University)

056
Successful FPGA Obsolescence Form, Fit, and Function Solution Using a MCM and DER™ to Implement Original Logic Design
Erick Spory, Global Circuit Innovations, Inc.

11:45 am

Conference Ends

1:00 pm Tee Time - "Scramble / Shotgun" Start

2018 IMAPS David Virissimo Memorial Charity Golf Outing
1:00pm Shotgun Start - "Scramble"

WeKoPa Golf Club
Fountain Hills, AZ

 

DOWNLOAD PROGRAM PDF

 


Registration Information: (Early Registration Deadline: February 7, 2018)

Member, Non-member, Speaker/Chair, Student and Chapter Officer registration fees include: access to all technical sessions, exhibits, meals, refreshment breaks, and one (1) DOWNLOAD of presentations; DOWNLOAD will contain the extended abstract and presentation as submitted by the presenter. DOWNLOAD will be emailed 15 approximately business days after the event. Also includes a one-year IMAPS individual membership or membership renewal at no additional charge which does not apply to corporate or affiliate memberships. All prices below are subject to change.

Type
Early Fee
Through 2/7/18
Advance/Onsite Fee
After 2/7/18
IMAPS Member
$800
$900
Non-Member
$900
$1000
Speaker
$550
$650
Chair
$550
$650
Student
$300
$400
Chapter Officer
$550
$650
Exhibits Only Pass w/ Lunch Included
$30
$30
Exhibits Only Pass NO Lunch Included
$0
$0
8x10 Exhibit (Member)
$1600
$1900
8x10 Exhibit (Non-Member)
$2300
$2600
Professional Development Course:
Each Course Registration is additional to the conference registration. Maximum of 1 morning course and one afternoon course can be selected. Attendees can opt for $0 exhibits only pass if they wish to take a PDC but NOT attend the conference/sessions.
$425
$475

 


Speaker Dates/Information:

  • Abstracts Deadline EXTENDED TO: November 8, 2017
  • Speaker Notification Emails: December 1, 2017
  • Extended Abstract Deadline: February 5, 2018
  • Hotel Reservation Deadline: February 7, 2018
  • Early Registration Deadline: February 7, 2018
  • Speaker Bios Due: February 15, 2018
  • Powerpoint/Presentation file for DOWNLOAD due not later than: March 8, 2018 (Last day of Conference)
  • Powerpoint/Presentation file used during session: Speaker's responsibility to bring to session on USB (recommended to have back-up on personal laptop or email to bschieman@imaps.org prior to event)
  • Technical Presentation Time: 30 minutes (25 to present; 5 for Q&A) - Keynotes: 45 minutes (40 to present; 5 for Q&A)

Presentation Format/Template:
IMAPS does not require you to use a conference powerpoint template.
You are able to use your regular company/preferred powerpoint templates.
Please include the IMAPS show name and dates on your template and/or an IMAPS logo.

Poster Session/Information
The poster session is planned to be an INTERACTIVE presentation. This means you do not start and complete a scheduled talk without interruption like in a regular/oral session. Speakers should have talking points and be at their poster throughout the entire session (Wednesday, March 7 from 5:30pm-6:30pm). You can "present" your scheduled materials, but more often the attendees will review your slides and ask questions. Or you can watch them and talk to them depending on which slide they are on. Authors may either print out each of their powerpoint slides on regular paper and tack them up in order, or prepare a large poster (or 2 even). Recommended poster size is typically 3x4 feet, with the max space on the board being 4 ft high x 8 ft wide. IMAPS staff will provide tacks to secure your print outs. The session is first-come-first-serve so there are not assigned poster boards/locations. POSTER SETUP FROM 4PM UNTIL 5:20PM on Wednesday, March 7.

Dress Code:
There is no officially "dress code" for IMAPS Conferences. We ask you to be BUSINESS CASUAL or whatever more you prefer. Most speakers tend to be in business pants and button down/company logo shirts (Women in dresses or the same). Suits, sport coats and ties are common as well. We do not recommend casual attire.

Session rooms will be equipped with:
Screen, projector, podium, IMAPS laptop (with Microsoft Windows and recent OFFICE suite), microphone, and slide remote/laser pointer.

All session presentations are 25 minutes followed by 5 minutes for Questions
You are required to load your powerpoint/presentation onto the session laptop yourself using your USB drive.
Speak with your session chair if you need assistance.

About the Session:
Sessions begin with Session Chairs making general announcements. Session Chairs will then introduce speakers by reading BIOs. Speaker will present for 25 minutes, followed by 5 minutes for questions. Session Chairs will thank the speakers. This process is repeated for each speaker in the session. Many sessions will take refreshment breaks (see program).

Photography is not permitted in the session rooms.

Silence all mobile phones during session attendance.

 

Housing
Hotel Reservation Deadline - February 7, 2018

Housing accommodations must be made directly to:

WeKoPa Resort & Casino
10438 North Fort McDowell Road
Scottsdale/Fountain Hills, AZ 85264

IMAPS Discounted Single/Double Room Rate: $179/night + taxes + fees

 

Book your hotel reservation today! We have reserved a block of rooms at the host hotel to accommodate our attendees. The discounted room rates are only available until the hotel deadline listed above, or until the room block sells out (and they often sell out early - before the expire dates). Reservations received after the noted deadline or after the room block has been filled may be subject to significantly higher rates. IMAPS room blocks at most hotels historically sell out ahead of the discount deadline, so we encourage you to make your hotel reservations quickly for the best price and availability.

Hotel Scams Alert!
All reservations should be made directly with the hotel and within the IMAPS room block. We are not using a housing company. If any person or firm contacts you and offers to handle your reservations, please beware. They are completely unauthorized and possibly fraudulent. The convention industry is currently plagued by such groups. If you use one of them and experience any problems, including lost deposits and no reservation when you arrive, IMAPS may not be able to assist you. Please be aware in particular of one of these unauthorized firms – Exhibition Housing Services – whose salespeople have falsely claimed to be calling from IMAPS.

The only way to book a room in the official IMAPS Housing Block using the reservations information above.

 

 

Device Packaging Sponsorship (Need to be ahead of your competition? Join this list today!)

PLATINUM PREMIER SPONSOR

Premier Platinum Sponsor: ASE US, Inc.
GOLD PREMIER SPONSORS
Premier Gold 
Sponsor - EMD Performance Materials
Premier Gold Sponsor - XYZTEC
SILVER PREMIER SPONSORS
Premier Silver Sponsor: Amkor Technology
Premier Silver Sponsor: NAMICS
Premier Silver Sponsor: Cadence
Premier Silver Sponsor: Mentor Graphics Premier Silver Sponsor: Kyocera
Corporate Sponsors
Corporate Sponsor - Dow Electronic Materials Corporate Sponsor - Technic
Mobile APP Sponsor: SETNA
SPTS - Corporate Sponsor
Corporate Sponsor - NGK NTK
Corporate Sponsor: Evatec
Corporate Sponsor: Applied Materials
Additional Event Sponsors

Mobile Station & Poster Session Sponsor: VEECO

Mobile Charging Station &
Poster Session Happy Hour

Poster Session Sponsor: SAMTEC

Poster Session Happy Hour

Break Sponsor - Intevac

Coffee Breaks (3)

Break Sponsor: 
TechSearch International

Coffee Break

Evening Panel & Reception Sponsor: Yield Engineering Systems, Inc.(YES)

Evening Panel & Reception

Break Sponsor: 
S3IP Binghamton University

Coffee Break

Sponsor: 
Kulicke and Soffa Industries

Bag Inserts & Web

 
Golf/Foundation Sponsors

"Birdie" Sponsor (1 hole):

DPC/GBC Premier Sponsor: ASE US, Inc.

Hole: 5 - Closest to Pin

"Birdie" Sponsor (1 hole):

EMD Performance Materials - Corporate Sponsor

Hole: 9 - Closest to Pin

"Birdie" Sponsor (1 hole):

Premier Gold Sponsor - XYZTEC

Hole: 15 - Closest to Pin

"Birdie" Sponsor (1 hole):

DPC/GBC Premier Sponsor: NAMICS

Hole: 12 - Longest Drive

"Birdie" Sponsor (1 hole):

Golf Hole Sponsor: Amkor Technology

Hole: 18 - Longest Putt

"Birdie" Sponsor (1 hole):

DPC Premier Gold Sponsor: Cadence

Hole: 1

"Birdie" Sponsor (1 hole):

Premier Silver Sponsor: Mentor Graphics

Hole: 2

"Birdie" Sponsor (1 hole):

Premier Silver Sponsor: Kyocera

Hole: 3

Golf Hole Sponsor: AGC Electronics America

Hole: 7 - Closest 2ND SHOT

Mobile Station & Poster Session Sponsor: VEECO

Hole: 6

Golf Sponsor: NxQ
Mask Aligners

Hole: 8

Golf Hole Sponsor: Nikon

Hole: 10

ASM Pacific - Hole Sponsor

Hole: 13

Corporate Sponsor - Technic

Hole: 14

Corporate Sponsor - Technic

Hole: 16

Golf Hole Sponsor: Advance Reproductions

Hole: 17

Golf Hole Sponsor: Dixon Golf

Hole: 4 - Straight Drive Competition
Hole: 11 - Hole-in-One Competition

Official Media Sponsors
3D Incites - Media Sponsor
Media Sponsor: Webcom - Electronics Protection
   

 



CORPORATE PREMIER MEMBERS
  • Amkor
  • ASE
  • Canon
  • EMD Performance Materials
  • Honeywell
  • Indium
  • Kester
  • Kyocera America
  • Master Bond
  • Micro Systems Technologies
  • MRSI
  • NGK NTK
  • Palomar
  • Plexus
  • Promex
  • Qualcomm
  • Quik-Pak
  • Raytheon
  • Specialty Coating Systems