15th International Conference and Exhibition on

WekoPa Resort
Fountain Hills, Arizona USA

IMAPS Device Packaging

Conference and Technical Workshops
March 5-7, 2019
Exhibition and Technology Showcase
March 5-6, 2019
Professional Development Courses
March 4, 2019
GBC Plenary Session
March 6, 2019
Device Packaging (Amkor Image)
Courtesy of Amkor Technology
Device Packaging (RDEDCOM image)
Courtesy of US Army RDEDCOM AMRDEC

General Chair:
Jon Aday
Illumina, Inc.

General Chair-Elect:
Rama Puligadda
Brewer Science

Past General Chair:
Peter Ramm
Fraunhofer EMFT Munich

(Website program will continue to updated if changes occur)




Courtesy of Amkor Technology

The Largest 2019 Conference Dedicated to...

Heterogeneous Integration & 3D IC;

Fan-Out, Wafer Level Packaging
& Flip Chip;

Engineered Micro Systems/Devices
); and

**New Track in 2019**

Courtesy of Amkor Technology



Thank you to our Premier PLATINUM Sponsor:

Thank you to our Premier GOLD Sponsors:

Premier Gold 
Sponsor - EMD Performance Materials
Premier Gold Sponsor - XYZTEC
Premier Gold Sponsor - JCET Group

Thank you to our Premier SILVER Sponsors:

Premier Silver Sponsor: Amkor Technology
Premier Silver Sponsor: NAMICS
Premier Silver Sponsor: Cadence
Premier Silver Sponsor: Mentor Graphics
Premier Silver Sponsor: Xperi / Invensas


2019 Conference Overview:

The 15th Annual Device Packaging Conference (DPC 2018) will be held in Fountain Hills, Arizona, on March 4-7, 2019. It is an international event organized by the International Microelectronics Assembly and Packaging Society (IMAPS).

The conference is a major forum for the exchange of knowledge and provides numerous technical, social and networking opportunities for meeting leading experts in these fields. The conference will attract a diverse group of people within industry and academia. It provides a chance for educational interactions across many different functional groups and experience levels. People who will benefit from this conference include: scientists, process engineers, product engineers, manufacturing engineers, professors, students, business managers, and sales & marketing professionals.


MONDAY, MARCH 4, 2019 -- Professional Development Courses (PDCs) & Welcome Reception
7:00 am - 7:00 pm
10:00 am - 12:00 pm
Morning Professional Development Courses (PDCs) - 10am-12pm

ROOM 103

PDC1: Introduction to Fan-Out Packaging
Course Leaders: John Hunt, ASE US, Inc.

ROOM 104

PDC2: Introduction to System in Package (SiP) - The Heterogeneous Integration Driver
Course Leaders: Mark Gerber, ASE US, Inc.

ROOM 105

PDC3: Flip Chip Package Technology and Assembly Processes
Course Leader: Tom Dory, Fujifilm Electronics Materials


PDC4: Polymers Used in Wafer Level Packaging

12:00 pm - 1:00 pm
LUNCH - Only provided for those attendees registered for both Morning AND Afternoon PDCs
1:00 pm - 3:00 pm
Early Afternoon Professional Development Courses (PDCs) - 1pm-3pm

ROOM 103

PDC5: Advances in Fan-Out Wafer Level Packaging (FOWLP)
Course Leader: Beth Keser, Intel Corporation

ROOM 104

PDC6: Fundamentals of 3D and 2.5D Packaging Integration
Course Leader: Urmi Ray

ROOM 105

PDC7: Introduction to Solder Flip Chip with an Emphasis on Cu Pillar
Course Leaders: Mark Gerber, ASE US, Inc.


PDC8: MEMS and nanoMEMS Packaging

3:00 pm - 3:30 pm
3:30 pm - 5:30 pm
Late Afternoon Professional Development Courses (PDCs) - 3:30pm-5:30pm

ROOM 103

PDC9: Fan-Out Wafer/Panel-Level Packaging and 3D IC Heterogeneous Integration
Course Leader: John Lau, ASM Pacific Technology

ROOM 104

PDC10: Advanced Microelectronics Packaging

ROOM 105

PDC11: Introduction to Failure Analysis in Semiconductor Package Assembly
Course Leaders: Tom Dory, Fujifilm Electronics Materials

ROOM 106

PDC12: 5G/mmWave Package Development Requirements and Solutions
Course Leader: Urmi Ray

5:30 pm - 7:30 pm

Welcome Reception (All Attendees Are Invited To Attend)

Thank you to our Welcome Reception Premier Sponsors:

Premier Gold 
Sponsor - EMD Performance Materials
Premier Gold Sponsor - XYZTEC
Premier Gold Sponsor - JCET Group
Premier Silver Sponsor: Amkor Technology
Premier Silver Sponsor: NAMICS
Premier Silver Sponsor: Cadence
Premier Silver Sponsor: Mentor Graphics
Premier Silver Sponsor: Xperi / Invensas




Premier Gold 
Sponsor - EMD Performance Materials


TUESDAY, MARCH 5, 2019 -- Morning Keynote Presentations

7:00 am -
7:00 pm


7:00 am -
8:00 am

Continental Breakfast Sponsored by:

Premier Gold 
Sponsor - EMD Performance Materials Premier Gold Sponsor - XYZTEC
Premier Gold Sponsor - JCET Group

8:00 am -
8:20 am

(ROOM 107-108)

General Chair:
Jon Aday, Illumina

Keynote Sessions Sponsored by:

SPTS - Corporate Sponsor


SPTS - Corporate Sponsor

8:20 am -
9:05 am

(ROOM 107-108)

Sensor Integration: Feynman or Moore?

Sensors are all around us: they are in cars, in smartphones, in factories, in pacemakers, in drones, in smart speakers and in many other places with the ultimate goal to sense and to monitor parameters of importance and interest in our daily environment. They play an essential bridge between electronic systems and the user or environment.

Today they already enable a multibillion dollar industry and they continue to create new business opportunities in many markets, such as automotive, consumer and personal electronics. Most importantly they are the enablers of emerging applications in Healthcare Industry and Industrial Internet of Things. There is no doubt that sensors will leave a sign in the new generation of home and factory robots, the autonomous cars, enabled by Artificial Intelligence. Thanks to their high reliability, high performances and low manufacturing cost, the most commercially successfull sensors available today are realized in silicon (i.e. Image Sensors and MEMS) and they use the same manufacturing techniques of the CMOS industry, whose evolution has been dictated by the famous G. Moore's law. Since the market for silicon sensors has been much smaller than overall semiconductor industry, sensors have been always classified as part of the so called "More than Moore" world. There are many books, article and publications on "More than Moore" subject, but considering the strong contribution to the sector given by the visionary Nobel Prize P. R. Feynman, envisioning the possibility to miniaturize the microsystems and to stack specialized silicon wafers to realize a complex versatile microsystem, time is come to see the Sensors as part of the "Feynman Roadmap" instead of "More than Moore" roadmap. After an extensive look-back over the current situation, this talk will address the future challenges of "Feynman Roadmap.”

KEYNOTE: Benedetto Vigna, STMicroelectronics - President, Analog, MEMS and Sensors Group

Benedetto Vigna, STMicroelectronics - President, Analog, MEMS and Sensors Group
Benedetto Vigna is STMicroelectronics' President, Analog, MEMS and Sensors Group, and has held this position since January 2016. He is a member of ST's Executive Committee since May 31st, 2018.

Vigna joined ST in 1995 and launched the Company's efforts in MEMS. Under his guidance, ST's MEMS sensors established the Company's leadership with large OEMs in motion-activated user interfaces. Vigna has piloted ST's successful moves into microphones, e-compasses, and touch-screen controllers, as well as environmental sensors, micro-actuators, industrial and automotive sensors, and low-power radios for IoT. Vigna's mandate was further expanded with analog ICs and RF products (2011) and smart-power devices for OEMs and mass market (2016). ST's Imaging division moved under his management in the fourth quarter of 2017.

Vigna has more than 200 patents on micromachining, authored numerous publications, and sits on the boards of several EU-funded programs. Vigna's contributions to the industry have been recognized with the MEMS Industry Group's Executive of the Year Award (2013), the European SEMI Award (2013), the IEEE Frederik Philips Award (2015), and Manager of the Year 2017 by German magazine Markt & Technik.

Benedetto Vigna was born in Potenza, Italy, in 1969, and graduated with a degree in Subnuclear Physics from the University of Pisa, Italy.

9:10 am -
9:55 am

(ROOM 107-108)

Life Reimagined: Technology and Business Innovations Driving an Autonomous World

The past few years have seen momentous changes in the automotive industry in areas such as predictive safety, infotainment and hybrid / electric technologies. As the industry gathers pace towards a world of driverless cars, the new norm in technological advances are not only in traditional domains such as power, braking etc. but also in mobile, home, office electronics and their applications to the automobiles we drive. Advanced driver assist systems, electrification and seamless connectivity to our devices near and far are the dominant trends driving the integration of highly innovative electronics in cars. This presentation will discuss how these technologies merge to serve the pilots of these advanced machines and the unique challenges that unifying these diverse domains provide. Innovations in advanced packaging platforms as well as traditional packaging platforms needed to power the electronic content underpinning the autonomous driving world will be discussed in the context of meeting new reliability, vehicle and functional safety as well as security requirements. NXP Semiconductors, as the #1 Global Automotive supplier, is ideally poised to understand the needs of the automotive market and produce innovations in collaboration with partners and suppliers. In addition to discussing the challenges, some of the unique solutions that NXP offers will also be presented as solution examples.

Keynote: Dr. Veer Dhandapani, NXP Semiconductors

Dr. Veer Dhandapani, NXP Semiconductors - Senior Director, Automotive Package Innovation
Veer Dhandapani is the Head of Automotive packaging at NXP Semiconductors and a Materials Scientist. He is currently responsible for new product and packaging technology development for NXP’s >$3.5B Automotive business. In this role, he oversees innovations in leaded and leadless packaging for Microprocessor, Analog, Sensor and Infotainment platforms. He brings 20 years of semiconductor industry experience across multiple strategic, supply chain and technology domains while at Philips Semiconductors, Motorola, Freescale and NXP. Veer Dhandapani has a Bachelor’s degree in Materials Engineering from the Indian Institute of Technology (IIT), Madras, India and a Ph.D. in Materials Science from the University of Cincinnati, OH.

9:55 am-10:00 am

General Chair:
Jon Aday, Illumina

10:00 am -
6:30 pm


10:00 am -
10:30 am

Break in the Exhibit Hall Sponsored by:

Break Sponsor: Pac Tech

Break Sponsor: Pac Tech


Premier Silver Sponsor: Amkor Technology



TUESDAY, MARCH 5, 2019 -- Morning Technical Sessions

3D Applications & Technologies

Flip Chip, Wafer Level Packaging & Fan-Out

Automotive Packaging


(ROOM 104-106)


Chair: Lars Boettcher, Fraunhofer IZM

(ROOM 107-108)


Chairs: Beth Keser, Intel Corp.; Scott Hayes, NXP

(ROOM 102-103)


Chairs: Prasad Dhond, Amkor Technology; Tu-Anh Tran, NXP

10:30 am - 11:00 am

3D IC: Overview of Industry Status
Vinayak Pandey, JCET Group

Cost Comparison of Panel Level and Wafer Level Fan-out Packaging
Amy Lujan, SavanSys Solutions LLC

Packaging Trends and Challenges for the Next Generation Automotive
Santosh Kumar, Yole Developpement (Lauranne Chemisky)

11:00 am - 11:30 am

Advanced Barrier and Seed Layer Deposition Enabling Multiple Type of TSVs Integration
Thierry Mourier, CEA-LETI (Mathilde Gottardi, Pierre-Emile Philip, Sophie Verrun,CEA-LETI; Gilles Romero, STMicroelectronics; Gaelle Guittet, Celine Doussot, Vincent Mevellec, Aveni)

New CAD Tools Feature for Virtual Prototyping
Steve Watt, Zuken USA, Inc. (Yoko Fujita, Kazunari Koga, Zuken Inc.)

LiDAR Packaging
Tim Nguyen, Velodyne LiDAR Inc.

11:30 am - 12:00 pm

Processing Through Glass Via (TGV) Interposers
Charles Woychik, i3 Electronics, Inc. (John Lauffer, Michael Gaige, William Wilson, James Carey, Matthew Neely, i3 Electronics, Inc.; Scott Pollard, Raj Parmar, Corning)

Versatility of Fan Out - Simple 2D to Complex 3D
John Hunt, ASE US Inc

Solder-Joint Reliability of BGA Packages in Automotive Applications
Burton Carpenter, NXP Semiconductors (Andrew Mawer, Mollie Benson, John Arthur, Betty Young)

12:00 pm - 12:30 pm

Through Glass Vias for hermetically sealed High Frequency Application
Kevin Kroehnert, Fraunhofer IZM (M.Wöhrmann, N.Juergensen, K.D.Lang, T.Galler, T.Chaloun, C. Waldschmidt, M. Schulz-Ruhtenberg, N. Ambrosius, R.Ostholt)

30µm Thick Cu RDL and Multi-layer RDL in WLCSP
Jacinta Amanlim, JCET Group (Seung Wook Yoon, Kenny Cao, Zhang Li, K.H. Tan)

Requirements off Automotive Tier1s and OEMs
Vinayak Pandey, JCET Group

12:30 pm -
2:00 pm

Lunch In The Exhibit Hall Sponsored by:
(Food served from 12:30 pm - 1:30 pm)

DPC/GBC Premier Sponsor: ASE US, Inc.



TUESDAY, MARCH 5, 2019 -- Afternoon Technical Sessions, Exhibit Hall Reception & Evening Keynote and Panel

3D Applications & Technologies

Flip Chip, Wafer Level Packaging & Fan-Out

Automotive Packaging


(ROOM 104-106)


Chairs: Dongshun Bai, Brewer Science; Rafiqul Islam, Cactus Materials

(ROOM 107-108)


Chairs: Jae Kyu Cho, GlobalFoundries; Nokibul Islam, JCET Group

(ROOM 102-103)

Chairs: Mark Gerber, ASE US; Linda Bal, TechSearch International

2:00 pm -
2:30 pm

High-Performance Heterogeneous Packaging Trends
Mike Kelly, Amkor Technology Inc. (Curtis Zwenger, Ruben Fuentes, Ron Huemoeller)

Ultra-low Warpage and Anhydride-free Liquid Compression Molding Materials for Advanced Semiconductor Packaging
Tim Champagne, Henkel Electronic Materials (Jay Chao, Kazuyasu Tanaka, Ramachandran Trichur, Rong Zhang)

Copper Ball Voids: Failure Mechanisms and Methods of Controlling at High Temperature Automotive Application

Chu-Chung Lee, NXP Semiconductor Inc. (TuAnh-Tran, Varughese Mathew, Rusli Ibrahim, Poh-Leng Eu)

2:30 pm -
3:00 pm

Development of High Density RDL Technologies for Panel Level Processing
Lars Boettcher, Fraunhofer IZM (S. Karaszkiewicz , F. Schein , R. Kahle, A. Ostmann)

Solder Paste Wicking in Socketable BGAs
Omkar Gupte, Georgia Institute of Technology (Vanessa Smet, Gregorio Murtagian, Rao Tummala)

Side Wettable Flanks for Leadless Automotive Packaging
Marc Mangrum, Amkor Technology, Inc.

3:00 pm -
3:30 pm

UV Projection Scanner Performance in Thick Resists for High Aspect Ratio Cu Pillars
William Vis, SUSS MicroTec Photonic Systems Inc. (Fabian Benthaus, Habib Hichri, Markus Arendt)

High Density Thin Organic Substrate for Advanced Flip Chip Package
Nokibul Islam, JCET Group (KH Tan, Tony Chen)

The Reliability of an Electroless Nickel, Electroless Palladium and Immersion Gold, Final Finish, Plating System can be Enhanced by Implementing Some Simple Drop in Process Changes
Kuldip Johal, Atotech GmbH (Rick Nichols, Sandra Nelle, Gustavo Ramos, Atotech GmbH; David Unruh, Intel Corp.)

3:30 pm -
4:00 pm

Break in Exhibit Hall Sponsored by:

Break Sponsor: Metalor

4:00 pm -
4:30 pm

Multi-chip module integration of Hybrid Silicon CMOS and GaN Technologies for RF Transceivers
Jennifer Kitchen, Arizona State University (Soroush Moallemi, Sumit Bhardwaj)

Investigation of a Proactive Glass Filler Removal in IC Substrate Build Up Films and its Effect on Topography and Copper Adhesion Reliability
Stefan Kempa, Atotech GmbH (Wolfgang Friz, Florian Gaul, Ellen Habig, Laurence Gregoriades, Roger Massey)

Rapid On-Substrate Curing of Thick Protective Package Sealing for Automotive Assembly
John Moore, Daetec LLC (Jevon Spencer)

4:30 pm -
5:00 pm

Wafer Level Submillimeter-wave Radar with Integrated Lens Antenna for 5G Application
Rafi Islam, Cactus Materials, Inc. (Ajit Dhamdhere, Wey Lyn Lee)

Fabrication and Assembly Processes for Custom and Commercial Flip-Chip Connections to Fine Pitch Indium Bump Arrays
Sherman Peek, Auburn University (Vaibhav Gupta, Bhargav Yelamanchili, Thomas Stegeman, Tamara Isaacs-Smith, John Sellers, David Tuckerman, Michael Hamilton)

Power Electronics Thermal Solutions using Thermally Conductive Polyimide Films
Rajesh Tripathi, DuPont (Sejin Im, Douglas Devoto, Joshua Major, Sreekant Narumanchi, Paul Paret, Xuhui Feng)

5:00 pm -
5:30 pm

Embedded SiP Modules for Next-Gen Heterogeneous ‘Power-Devices’
Kevin Moody, ACCESS Technologies, USA (Nick Stukan)

Low Temperature Flip Chip Bonding Technology Applicable to Flexible Hybrid Electronics in the IoT Era
Hiroshi Komatsu, CONNECTEC JAPAN Corp. (Hidekazu Machida, Nozomi Shimoishizaka)  

Performance Comparison Between Surface-mount and Embedded Power Modules
Gerald Weis, AT&S Austria Technologie und Systemtechnik Aktiengesellschaft

5:30 pm -
6:30 pm

Exhibit Hall Reception
Sponsored by:

MacDermid Alpha Electronics Solutions - Reception Sponsor

Exhibit Reception Sponsor: JX Nippon Mining & Metals

Corporate Sponsor - Technic
6:30 pm -
8:30 pm

(ROOM 107-108)


Session & Refreshments Sponsored by:

Corporate Sponsor: Evatec


Directions in Advanced Packaging Technology

This talk will address the role of packaging in enabling Heterogeneous Integration and will focus primarily on the technology evolution of package interconnect densities & future challenges in interconnect density scaling.

Keynote: Sriram Srinivasan, Intel Corporation - Principal Engineer

Sriram Srinivasan, Intel Corporation - Principal Engineer
Sriram Srinivasan is a Principal Engineer with Intel Corporation responsible for package architecture and technology definition for Intel products. He has been with Intel-Packaging for 18 years. His focus is on Silicon-package-platform co-design to deliver optimized product and technology. He has numerous patents in the areas of package design, assembly process and interconnect technologies. Sriram holds a Masters in Chemical Engineering from University of Kansas.


Heterogenous Integration: Why Now?

The discussion will focus on the drivers for heterogeneous integration and types of advanced packages being introduced today and in the future. Challenges and issues for these packaging solutions will be discussed.

E. Jan Vardaman, TechSearch International, Inc.

Bill Chen, ASE
Nokibul Islam, JCET Group
Mike Kelly, Amkor Technology
Dan Oh, Samsung Electronics
Rajendra (Raj) Pendse, Facebook Reality Labs
Sriram Srinivasan, Intel Corporation


Panel Session & Refreshments Sponsored by:

Corporate Sponsor: Evatec


MacDermid Alpha Electronics Solutions - Reception Sponsor


WEDNESDAY, MARCH 6, 2019 -- GBC Keynote & Plenary Session

7:00 am -
6:00 pm


7:00 am -
8:00 am

Continental Breakfast Sponsored by:

Premier Gold 
Sponsor - EMD Performance Materials Premier Gold Sponsor - XYZTEC
Premier Gold Sponsor - JCET Group


(ROOM 107-108)

Welcome to the Global Business Council (GBC) Keynote & Plenary Session on

8:00am - 8:15am

(ROOM 107-108)

GBC Chairs:
Lee Smith, (UTAC) United Test & Assembly Center; Rich Rice, ASE US, Inc.; Thomas Goodman, Izinus

8:15am - 9:00am

(ROOM 107-108)

Cars and Clouds: New Drivers for Efficient Power Management

The electrification of transportation and the continued expansion of cloud based computing are two drivers for optimizing power efficiency. The automotive power requirements focus on highly efficient transfer from DC to AC (and vice versa), at very high power levels. Current IGBT switching devices are packaged in large modules with extensive cooling capacities. Reductions in size/weight require increased efficiency at higher frequency and current density. The desire for higher efficiency in datacenters is aimed at cost reduction of the total compute environment. Each individual server requires the most efficient power conversion from high voltage distribution lines to very low voltage boards. Switching devices again are packaged in modules, operating at very high power density, requiring co-optimization of devices, connections and packages. To realize the desired combination of size, speed and density, wide bandgap materials may be needed to advance the roadmap of these power management products. We will review some of the recent progress and challenges in materials innovation to optimize device and package and circuit.

GBC Keynote: Michael Seddon, ON Semiconductor

Michael Seddon, ON Semiconductor - Technical Fellow, Corporate R & D
Mike Seddon began his career with Motorola in 1992 which spun off and formed ON Semiconductor in 1999. Throughout his career, Mike has been involved in developing a wide range of advanced packaging technologies on a global basis including:

• ASIC and packaging solutions for the medical, computing, industrial, automotive and consumer industries • Wide range of bumping and plating technologies • Vertical Cavity Surface Emitting Lasers • Advanced Materials Development • Through Silicon Vias, advanced wafer thinning technologies • Piezoelectric Materials • Manager of the Advanced Interconnect Development Lab

Mike is currently responsible for creating new packaging technology platforms including:

• Next generation materials and interconnect development • Ultra thin wafers • Cu Power Metallization • Low Cost TSV • Advanced die singulation techniques

Mike currently has 47 patents issued and >40 patents pending.

9:00am - 9:30am

Packaging Trends and Challenges for Power Devices
Jan Vardaman, TechSearch International
Power devices are experiencing strong growth driven by demand in a variety of areas. Applications including energy generation and infrastructure, electric and hybrid vehicles, electric vehicle charging, datacenters, industrial automation, smart cities and buildings, home appliances, and transportation are driving demand for power devices. While many companies continue to expand production of silicon-based power devices, there is also demand for devices based on new wide band gap (WBG) materials such as silicon carbide (SiC) and gallium nitride (GaN). Driven by the need for increased power density and system efficiency, these WBG materials are being adopted in many applications and may require new packages, materials, and assembly methods. This presentation describes package trends and discusses some of the challenges faced.

9:30am - 10:00am

Modern Cell Phone Power Electronics Overview and Future Challenges
Todd Sutton, Qualcomm
The second largest thing in your cell phone is the battery and roughly half of the electronics is associated with power management. This talk will provide an overview of these systems and shed some light on the challenges in the not so distant away future.

10:00 am -
4:00 pm


10:00 am - 10:45 am

Break in the Exhibit Hall

10:45am - 11:15am

Power Module Packaging: Market & Technology Trends
Elena Barbarini, SystemPlus Consulting; Claire Troadec, Yole Développement
In recent years, several new power module designs have emerged, principally driven by the severely challenging requirements for high power density and integration from the automotive industry. Indeed, electric and hybrid cars are the best example of technology innovation in the design of power modules. The Toyota Prius’ fourth generation double-sided cooling power modules might be the most well-known example. Yet today many other module manufacturers are also proposing new designs that move away from conventional power module layers and technologies. In our presentation, we will start with market trends and illustrate how industrial applications still remain the biggest part of the power module market. We will then demonstrate that the automotive industry is leading in technological innovations in packaging, helping and accelerating the implementation of these new technologies thanks to high manufacturing volumes. We will detail these technology trends by providing real teardown and cost analysis of various power modules. We will explain how they are creating opportunities for some material suppliers, and at the same time, are transforming today’s businesses for power packaging.

11:15am - 11:45am

IC Market Update and China Impact Analysis
Bill McClean, IC Insights
A high level of uncertainty looms over the global economy and sales of smartphones are beginning to saturate. However, the Internet of Things, driver assisted autos, and AI hold promise for the future. In order to make sense out of the current turmoil, a top-down analysis of the IC market will be given and include trends in worldwide GDP growth, electronic system sales, and semiconductor industry capital spending. A critical look at China’s ambitions to become a bigger player in the IC industry will also be presented.

11:45am - 12:00pm

GBC Closing Remarks

12:00 pm -
1:30 pm

Lunch in the Exhibit Hall Sponsored by:
(Food served from 12:00 pm - 1:00 pm)

DPC/GBC Premier Sponsor: ASE US, Inc.



WEDNESDAY, MARCH 6, 2019 -- Afternoon Sessions

3D Applications & Technologies

Flip Chip, Wafer Level Packaging & Fan-Out

Engineered Micro Systems/Devices
(including MEMS & Sensors)


(ROOM 104-106)


Chairs: Rahul Jain, Intel Corporation; Stevan Hunter, ON Semiconductor

(ROOM 107-108)


Chairs: Amy Lujan, SavanSys; Rebecca Schmidt, DOW

(ROOM 102-103)


Chairs: Li-Anne Liew, National Institute of Standards and Technology & University of Colorado, Boulder; Robert M. Weikle II, University of Virginia

1:30 pm -
2:00 pm

What is Driving the TSV Business: Market & Technology Trends
Santosh Kumar, Yole Developpement

Design, Processes & Technology Co-design Methodology for Advanced Package Assembly in HVM

Diane Peng, Quantenna Communication (Baqar Tabrez)

Compact Labyrinth Element Acoustic Metamaterials for Broadband Low-frequency Attenuation
Fuxi Zhang, Auburn University (George Flowers, Edmon Perkins, Robert Dean, Jeffrey Suhling, Jordan Roberts)

2:00 pm -
2:30 pm

The Bifurcation of Advanced IC Packaging
John Park, Cadence Design Systems

Enabling Early and Fast Thermal Simulation for 3D Multi-Die System Designs
Tunir Dey, Zuken, Inc. (Kazunari Koga, Humair Mandavia)

The Advantages of Using 3D Printing to Manufacture Test Fixtures for Evaluating MEMS Devices
Arthur Bond, Auburn University (Brent Bottenfield, Mark Adams, Robert Dean)

2:30 pm -
3:00 pm

System-level, Post-layout Electrical Analysis for High-density Advanced Packaging
Tarek Ramadan, Mentor a Siemens Business (Dusan Petranovic)

Formaldehyde-Free Electroless Copper Solution for Next Generation Substrates
Stefan Kempa, Atotech GmbH (Christian Wendeln, Edith Steinhauser, Lutz Stamp, Bexy Dosse-Gomez, Elisa Langhammer, Sebastian Reiber, Sebastian Duennebeil, Sandra Roeseler, Roger Massey)

Additive Dielectric Microstructures
Kurt Christenson, Optomec

3:00 pm -
4:00 pm

Break in Exhibit Hall

4:00 pm -
4:30 pm

Thinking in 3D - The New Architecture
Javi DeLaCruz, XPERI Corporation

Automated Daisy Chain Generation and Verification

Tom Whipple, Viasat (Doug Mathews, Viasat; Tom Hoang, Zuken)

Passive, Non-fluid Damping Materials for Micromachined Vibration Isolators
Brent Bottenfield, Auburn University (Artie Bond, Mark Adams, Robert Dean)

4:30 pm -
5:00 pm

Photosensitive Glass-Ceramics for Heterogeneous Integration

Jeb Flemming, 3D Glass Solutions (Kyle McWethy, Tim Mezel, Luis Chenoweth, Carrie Schmidt)

CerapheneTM - a Stack of CVD Graphene and Ceramic Materials (2D) for Thermal Management of 2.5D/3D Packages
Rafiqul Islam, Cactus Materials, Inc. (Ajit Dhamdhere, Wey Lyn Lee)

Organic Substrate Technologies for Fingerprint Sensors
Shengmin Wen, Synaptics Inc. (Jason Goodelle)

5:00 pm -
5:30 pm

Material Design Advancement Create Multifunctional Materials for Single-Layer Temporary Bonding and Debonding
Luke Prenger, Brewer Science (Xiao Liu, Qi Wu, Rama Puligadda)

Microbump Processing for 3D IC Integration
Feng Li, University of Idaho (Qianyi Li, Andrew Owens)

Isolated Interposers for MEMS Sensors
Michael Kranz, EngeniusMicro (Michael Whitley, Brian English, Mark Adams, Robert Dean, Brent Bottenfield, Artie Bond)


Device Packaging Poster Session

5:30 pm -
6:30 pm


Outside On Patio Overlooking Desert: 5:30 pm - 6:30 pm
(Poster Presenter Setup - 4:00 pm - 5:25 pm)

Poster Session & Happy Hour Sponsored by:

Corporate Sponsor - DuPont Electronics & Imaging
Corporate Sponsor: Applied Materials



Can Electrolytic Capacitors Meet the Demands of High Reliability Applications?
Greg Caswell, DfR Solutions (Paul Parker)

A New Photosensitive Dielectric Material for High-Density RDL with Ultra-Small Photo-Vias and High Reliability
Daichi Okamoto, Taiyo Ink Mfg. Co. Ltd. (Yoko Shibasaki, Daisuke Shibata, Tadahiko Hanada)

High-Throughput Precise Dotting in Electronics Assembly
Hanzhuang Liang, Nordson Asymtek (Akira Morita, Brian Chung)

Advanced Adhesion Promotor System for IC Substrate Packaging
Neal Wood, Atotech GmbH (Thomas Thomas, Tatjana Cukic, Fabian Michalik, Valentina Belova-Magri, Michael Merschky, Xiaoting, Felix Tang, Wonjin Cho, Patrick Brooks)

Direct Die-placement Technology for Component Attach in Thin and Lightweight Electronics
David Grierson, systeMECH, Inc. (Kevin Turner, Wilfried Bair)

Optimising Surface Chemistry After Plasma Dicing
Stewart Fulton, Janet Hopkins, SPTS Technologies Newport (Oliver Ansell, SPTS Technologies Newport; Michael Phenis, Don Pfettscher, Richie Peters, Mark Sistern, Versum Materials US, LLC)

A Technique for Reducing System Form Factor in Electronic Systems
Benjamin Rhea, Auburn University (R. Chase Harrison, Robert Dean)

Semiconductor Packaging and CDM ESD Risk

Stevan Hunter, ON Semiconductor (Nicholas Vincetic, Arizona State University)

Interfacial Degradation of Copper Wire Bond due to Growth of Cu9Al4 phase

Stevan Hunter, ON Semiconductor (Subramani Manoharan, Chandradip Patel, Patrick McCluskey, CALCE, University of Maryland)

Rapid Dissolving of Dry Film Resist (DFR) Using Green Products
John Moore, Daetec LLC

Packaging Constraints and Parasitic Modeling in High Frequency Medium Power Amplifiers
Soroush Moallemi, Arizona State University (Jennifer Kitchen)

Applying PCB Sensor Technology to Nutrition Sciences
Robert Dean, Auburn University

***Also in session TA2:
Cost Comparison of Panel Level and Wafer Level Fan-out Packaging
Amy Lujan, SavanSys Solutions LLC

***Also in session WP3:
Compact Labyrinth Element Acoustic Metamaterials for Broadband Low-frequency Attenuation
Fuxi Zhang, Auburn University (George Flowers, Edmon Perkins, Robert Dean, Jeffrey Suhling, Jordan Roberts)

***Also in session WP3:
Organic Substrate Technologies for Fingerprint Sensors
Shengmin Wen, Synaptics Inc. (Jason Goodelle)

***Also in session WP2:
Design, Processes & Technology Co-design Methodology for Advanced Package Assembly in HVM

Diane Peng, Quantenna Communication (Baqar Tabrez)

***Also in session TP2:
Impact of Glass Filler Removal on Electroless Copper Performance in Advanced Build-up-films
Stefan Kempa, Atotech GmbH (Wolfgang Friz, Florian Gaul, Ellen Habig, Laurence Gregoriades, Roger Massey)

***Also in session WP2:
Formaldehyde-Free Electroless Copper Solution for Next Generation Substrates
Stefan Kempa, Atotech GmbH (Christian Wendeln, Edith Steinhauser, Lutz Stamp, Bexy Dosse-Gomez, Elisa Langhammer, Sebastian Reiber, Sebastian Duennebeil, Sandra Roeseler, Roger Massey)

(additional abstracts in regular session will also be invited to participate)
In event of inclement weather, the poster session will be held in the foyer of the conference center


Corporate Sponsor - DuPont Electronics & Imaging

6:30 pm -
8:00 pm

3D Incites - Media Sponsor
2019 3D InCites Awards Ceremony and
10th Anniversary Barbeque

Hosted by IMAPS

Immediately Following the Poster Session - Outside On Patio Overlooking Desert


Please join us for an evening of fun, games, and prizes as we celebrate the winners of the 2019 3D InCites Awards and celebrate the 10th Anniversary of 3D InCites with the 3D InCites Awards Ceremony Barbeque on Wednesday, March 6, from 6:00 - 8:00 PM.

• Watch the on-site creation of the 2019 mural. This year’s theme is "Celebrating 25 Years of Advanced Packaging Innovation." Donate $500 to own a milestone on the timeline.
• Compete in the Awards Ceremony Quiz during the ceremony and win a prize!
• Capture memories with your friends and colleagues at our photo booth
• Enjoy a fully catered Wrangler barbeque buffet, including beer, wine, and iced tea.

New this year, is the 3D InCites SemiSister™ Award -- awarded to an individual or company that demonstrates the most gender diversity and inclusion.

The 2019 3D InCites Awards will be presented in the following categories:

  • Device of the Year
  • Process of the Year
  • Device Manufacturer of the Year
  • Startup of the Year
  • Equipment Supplier of the Year
  • Materials Supplier of the Year
  • EDA Provider of the Year
  • Research Institute of the Year
  • Engineer of the Year
  • SemiSister of the Year

Cast your votes here by February 28th

A portion of the proceeds from the event will benefit two charities: the IMAPS Microelectronics Foundation, which exists to support student activities related to the study of microelectronic packaging, interconnect and assembly; and Phoenix Children’s Hospital pediatric oncology programs, the only institution in Arizona conducting Phase I trials, giving pediatric cancer patients access to the latest and most advanced treatments available.

(Participation is included in your registration fee, but space is limited. Please reserve your spot when you register.)

3D Incites - Media Sponsor


Premier Silver Sponsor: Xperi / Invensas


THURSDAY, MARCH 7, 2019 -- Keynote Presentations

7:00 am -
11:30 am


7:00 am -
8:00 am

Continental Breakfast Sponsored by:

Premier Gold 
Sponsor - EMD Performance Materials Premier Gold Sponsor - XYZTEC
Premier Gold Sponsor - JCET Group

8:00 am -
8:45 am

(ROOM 107-108)

Keynote Sessions Sponsored by:

SPTS - Corporate Sponsor

(ROOM 107-108)

Package Technologies for the 4th Industrial Revolution

The 4th Industrial Revolution with artificial intelligence, autonomous vehicles, robotics, and biotechnology demands power efficient computing devices such as GPU, TPU, and FPGA. To further enhance the performance, advanced System-in-Package (SiP) such as 2.5D and 3D integration technologies are needed to satisfy the high computing and power efficiency requirements.

High-performance SiP systems must integrate advanced packaging technologies with both complex signal/power integrity and enhanced thermal solutions. In addition, package developers need to work closely with chip designers at a very early stage of the product development to achieve the target performance and reliability.

In this Keynote, Dr. Oh, Vice President of Package Development at Samsung Electronics will start with an overview of the evolution and importance of package technology to meet the needs of emerging high-end computing platforms. Furthermore, a high-performance SiP system with a Fan Out (FO) package is introduced for power efficient mobile platforms. In addition, the extension of the FO package for high-end server applications is discussed. Finally, pros and cons of the FO package compared to 2.5D Si-interposer are discussed.

Keynote: Dr. Dan Oh, Samsung Electronics - Head of Packaging Development Department

Dr. Dan Oh, Samsung Electronics - Head of Packaging Development Department
Dan Oh joined Samsung Electronics as an engineering VP to develop new package solutions for next generation IC products in 2016. He is currently the head of Package Development department in Test & System Package organization. Package Development department develops the packages for all Samsung products including memory, system LSI, and foundry business units. Prior to Samsung, Dr. Oh was a Signal and Power Integrity (Si/Pi) Architect at Intel Programmable Solutions Group where he is responsible for leading cross functional SI/PI co-design teams including IC design, packaging, and product engineering as well as driving the overall Si/Pi technical direction. Dr. Oh also worked at Rambus as a Technical Director where he defined the signaling roadmap, supported system definition of new product proposals, and drove IP development for innovative signaling solutions. He received his Ph.D. in Electrical Engineering from the University of Illinois at Urbana-Champaign. He has numerous patents and papers in the areas of high-speed I/O modeling, simulation, and design. He is the lead author of the book “High-speed Signaling: Jitter Modeling Analysis, and Budgeting,” and also served on the technical program committees of leading conferences such as IEEE EPEPS, IEEE ECTC, IEEE EMC SIPI, and DesignCon.

8:45 am -
9:30 am

(ROOM 107-108)

New Directions in Si/Packaging for AR/VR Hardware

The AR/VR hardware of tomorrow is set to carve out a new trajectory in power/performance and form factor quite unlike anything we have seen in the realm of modern-day consumer hardware and rivaled only by the human brain. This will range from logic, memory and sensor devices powered with AI for ultralow power consumption, life like display and imaging technologies and innovative packaging to enable integration in constrained form factors – it will include new 3D stacking architectures, fan out wafer level packaging, heterogeneous integration, low loss dielectric materials and predictive tools for performance and reliability modeling. We will look at the packaging challenges from a holistic system-package-Si view point and present new approaches and solutions being developed to address the challenges; and finally, a vision of what the future holds in the 5-10-year horizon.

Keynote: Dr. Rajendra (Raj) D. Pendse, Facebook Reality Labs

Dr. Rajendra (Raj) D. Pendse, Facebook Reality Labs - Silicon/Packaging Architect
Dr. Raj Pendse is Si/Packaging Architect at Facebook Reality Labs (FRL) and leads the development of advanced solutions for AR/VR hardware. Raj was previously Vice President of Package Engineering at Qualcomm and played various leadership roles in Package development at STATS ChipPAC, Hewlett-Packard Labs and National Semiconductor. Raj’s work has spanned the gamut from packaging of high-end microprocessors, ASIC and graphics products to low-cost packaging solutions for logic and analog devices that find use in mobile phones and consumer products. His most recent focus has been on 3D and Wafer Level Packaging for AR/VR hardware. Raj completed his BS in Materials Science from IIT Bombay with Top in Class honors and his Doctorate in Materials Science from UC Berkeley.

9:30 am -
9:45 am

Break in the Foyer



THURSDAY, MARCH 7, 2019 -- Morning Sessions

3D Applications & Technologies

Flip Chip, Wafer Level Packaging & Fan-Out

Engineered Micro Systems/Devices
(including MEMS & Sensors)


(ROOM 104-106)


Chairs: Peter Ramm, Fraunhofer EMFT; Diane Scheele, Versum Materials

(ROOM 107-108)


Chairs: Kevin Martin, Atotech USA; Linda Bal, TechSearch International

(ROOM 102-103)


Chairs: Keaton Rhea, Auburn University; Zhangming Zhou, Qualcomm Inc.

9:45 am -
10:15 am

Temporary and Permanent Bonding Enables 3D Integration of Ultrathin Wafers
Thomas Uhrmann, EVG (Elisabeth Brandl, Mariana Pires, Stefan Jung, Juergen Burggraf, Matthew Koch)

Quick Prototyping Design for More than Moore Era
Yoko Fujita Zuken Inc. (Kazukani Koga, Zuken Inc.; Shintaro Ohtani, Daisuke TsuTsui, Socionext Inc.)

Thermal Characterization of Quasi-Vertical GaAs Schottky Diodes Integrated on Silicon Using Thermoreflectance and Electrical Transient Measurements
Robert M. Weikle II, University of Virginia (S. Nadri, C.M. Moore, N.D. Sauber, L. Xie, M.E. Cyberey, N. Scott Barker, A.W. Lichtenberger, M Zebarjadi)

10:15 am -
10:45 am

Key Enabling Materials for 3DIC Fabrication and Device Performance
Michael Gallagher, DuPont Electronics and Imaging (Ed Anzures, Robert Auger, Rosemary Bell, Paul, Berry, Hua Dong, Michelle Ho, Joe Lachowski, Yil-Hak Lee, Masaki Kondo, Julia Kozhukh, Paul Morganelli, Janet Okada, Ravi Pokhrel, Jonathan Prange, Matthew VanHanehem)

Semiconductor-on-Polymer Wafer Level Chip Scale Packaging
Doug Hackler, American Semiconductor (Dale Wilson, American Semiconductor; Edward Prack, MASIP, LLC)

A Quasi-optical Testbed for Terahertz On-Wafer Device and Circuit Characterization

Yiran Cui, Arizona State University (Georgios Trichopoulos)

10:45 am -11:15 am

Electroplating Fundamentals for Coplanarity Improvement
Marvin Bernt, Applied Materials

Physical and Electrical Characterization of Polymers Using Low Pressure Vacuum Cure for Fan-Out Wafer Level Packaging
Bill Moffat, Yield Engineering Systems (Ken Sautter, Charadutta Galande, Kaushal Singh, Zia Karim)

A PCB Sensor for Magnetic Materials
Robert Dean, Auburn University (Lauren Beckingham, Michael Bozack)

11:15 am -
11:45 am

Dicing Tape Performance in a Plasma Dicing Environment
Stewart Fulton, SPTS Technologies Newport (Oliver Ansell, Janet Hopkins, SPTS Technologies Newport; Taku Umemoto, Takuo Nishida, LINTEC Advanced Technologies (Europe) GmbH)

Process Control for Advanced Packaging Metallization
Eugene Shalyt, ECI Technology (Michael Pavlov, Danni Lin, Michael MacEwan, Helen Lu, Paul Okagbare)

Ti-Pd-Au as a Sacrificial Layer, Buried Interconnect and Etch Mask for Fabrication of Polyimide Surface Micromachined Micropumps
Li- Anne Liew, National Institute of Standards and Technology & University of Colorado (Ching-Yi Lin, Collin Coolidge, Y.C. Lee)

11:45 am

Conference Ends

1:30 pm Tee Time - "Scramble / Shotgun" Start

2019 IMAPS David Virissimo Memorial Charity Golf Outing
1:30pm Shotgun Start - "Scramble"

WeKoPa Golf Club
Fountain Hills, AZ



Registration Information:

Member, Non-member, Speaker/Chair, Student and Chapter Officer registration fees include: access to all technical sessions, exhibits, meals, refreshment breaks, and one (1) DOWNLOAD of presentations; DOWNLOAD will contain the extended abstract and presentation as submitted by the presenter. DOWNLOAD will be emailed 15 approximately business days after the event. Also includes a one-year IMAPS individual membership or membership renewal at no additional charge which does not apply to corporate or affiliate memberships. All prices below are subject to change.

Early Fee
Through 2/1/19
Advance/Onsite Fee
After 2/1/19
IMAPS Member
Chapter Officer
Exhibits Only Pass w/ Lunch Included
Exhibits Only Pass NO Lunch Included
8x10 Exhibit (Member)
8x10 Exhibit (Non-Member)
Professional Development Course:
Each Course Registration is additional to the conference registration. Maximum of 1 morning course and one afternoon course can be selected. Attendees can opt for $0 exhibits only pass if they wish to take a PDC but NOT attend the conference/sessions.


Speaker Dates/Information:

    • Abstracts Deadline now due: November 21, 2018
    • Speaker Notification Emails: December 7, 2018
    • Extended Abstract Deadline: January 31, 2019
    • Hotel Reservation Deadline: February 1, 2019
    • Early Registration Deadline: February 1, 2019
    • Speaker Bios Due: February 15, 2019
    • Powerpoint/Presentation file for DOWNLOAD due not later than: March 7, 2019 (Last day of Conference)
    • Powerpoint/Presentation file used during session: Speaker's responsibility to bring to session on USB (recommended to have back-up on personal laptop or email to prior to event)
    • Technical Presentation Time: 30 minutes (25 to present; 5 for Q&A) - Keynotes: 45 minutes (40 to present; 5 for Q&A)

    Presentation Format/Template:
    IMAPS does not require you to use a conference powerpoint template.
    You are able to use your regular company/preferred powerpoint templates.
    Please include the IMAPS show name and dates on your template and/or an IMAPS logo.

    Poster Session/Information
    The poster session is planned to be an INTERACTIVE presentation. This means you do not start and complete a scheduled talk without interruption like in a regular/oral session. Speakers should have talking points and be at their poster throughout the entire session (Wednesday, March 6 from 5:30pm-6:30pm TBD). You can "present" your scheduled materials, but more often the attendees will review your slides and ask questions. Or you can watch them and talk to them depending on which slide they are on. Authors may either print out each of their powerpoint slides on regular paper and tack them up in order, or prepare a large poster (or 2 even). Recommended poster size is typically 3x4 feet, with the max space on the board being 4 ft high x 8 ft wide. IMAPS staff will provide tacks to secure your print outs. The session is first-come-first-serve so there are not assigned poster boards/locations. POSTER SETUP FROM 4PM UNTIL 5:00PM on Wednesday, March 6 (TBD).

    Dress Code:
    There is no official "dress code" for IMAPS Conferences. We ask you to be BUSINESS CASUAL or whatever more you prefer. We do not recommend casual attire.

    Session rooms will be equipped with:
    Screen, projector, podium, IMAPS laptop (with Microsoft Windows and recent OFFICE suite), microphone, and slide remote/laser pointer.

    All session presentations are 25 minutes followed by 5 minutes for Questions
    You are required to load your powerpoint/presentation onto the session laptop yourself using your USB drive.
    Speak with your session chair if you need assistance.

    About the Session:
    Sessions begin with Session Chairs making general announcements. Session Chairs will then introduce speakers by reading BIOs. Speaker will present for 25 minutes, followed by 5 minutes for questions. Session Chairs will thank the speakers. This process is repeated for each speaker in the session. Many sessions will take refreshment breaks (see program).

    Photography is not permitted in the session rooms.

    Silence all mobile phones during session attendance.




WeKoPa Resort & Casino
10438 North Fort McDowell Road
Scottsdale/Fountain Hills, AZ 85264



Device Packaging Sponsorship (Need to be ahead of your competition? Join this list today!)


Premier Gold 
Sponsor - EMD Performance Materials
Premier Gold Sponsor - XYZTEC
Premier Gold Sponsor - JCET Group
Premier Silver Sponsor: Amkor Technology
Premier Silver Sponsor: NAMICS
Premier Silver Sponsor: Cadence
Premier Silver Sponsor: Mentor Graphics
Premier Silver Sponsor: Xperi / Invensas
Corporate Sponsors
Corporate Sponsor - NGK NTK
Corporate Sponsor - DuPont Electronics & Imaging
SPTS - Corporate Sponsor
Mobile APP Sponsor: SETNA
MacDermid Alpha Electronics Solutions - Corporate Sponsor
Corporate Sponsor - Technic
Corporate Sponsor: Pac Tech
Corporate Sponsor: Evatec
Corporate Sponsor: Applied Materials
Additional Event Sponsors

Break Sponsor: Metalor

Coffee Break

Exhibit Reception Sponsor: JX Nippon Mining & Metals

Exhibit Reception

Notebook Sponsor: SMART Microsystems

Session Notebooks/Pens

Golf/Foundation Sponsors

"Birdie" Sponsor:

DPC/GBC Premier Sponsor: ASE US, Inc.

Hole: 5 - Closest to Pin

"Birdie" Sponsor:

EMD Performance Materials - Corporate Sponsor

Hole: 9 - Closest to Pin

"Birdie" Sponsor:

Premier Gold Sponsor - XYZTEC

Hole: 15 - Closest to Pin

"Birdie" Sponsor:

Premier Gold Sponsor - JCET Group

Hole: 7 - Closest 2ND SHOT

"Birdie" Sponsor:

Golf Hole Sponsor: Amkor Technology

Hole: 18 - Longest Putt

"Birdie" Sponsor:

DPC/GBC Premier Sponsor: NAMICS

Hole: 12 - Longest Drive

"Birdie" Sponsor:

DPC Premier Gold Sponsor: Cadence

Hole: 1

"Birdie" Sponsor (1 hole):

Premier Silver Sponsor: Mentor Graphics

Hole: 2

"Birdie" Sponsor:

Premier Silver Sponsor: Xperi / Invensas

Hole: 3

ASM Pacific - Hole Sponsor

Hole: 13

Golf Hole Sponsor: Advance Reproductions

Hole: 6

Golf Sponsor: NxQ
Mask Aligners

Hole: 8

Golf Hole Sponsor: Nikon

Hole: 10

Exhibit Reception Sponsor: JX Nippon Mining & Metals

Hole: 14

Golf Sponsor - Kite Rocket

Hole: 16

Golf Sponsor - SUSS Microtec

Hole: 17

Golf Hole Sponsor: Dixon Golf

Hole: 4 - Straight Drive Competition
Hole: 11 - Hole-in-One Competition

Official Media Sponsors
3D Incites - Media Sponsor
Media Sponsor: MEPTEC


  • Amkor
  • ASE
  • Canon
  • Corning
  • EMD Performance Materials
  • Honeywell
  • Indium
  • Kester
  • Kyocera America
  • Master Bond
  • Micro Systems Technologies
  • MRSI
  • Palomar
  • Promex
  • Qualcomm
  • Quik-Pak
  • Raytheon
  • Rochester Electronics
  • Specialty Coating Systems
  • Spectrum Semiconductor Materials
  • Technic