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Topical Workshop & Exhibition on
Flip Chip Technology

Technical Program

Sponsored by:
IMAPS
International Microelectronics And Packaging Society
"Everything in electronics between the chip and the system!"

June 21-24, 2004
Austin Marriott at the Capitol
Austin, Texas 78701

co-located with the Global Business Council (GBC) Summer Conference, June 21st - www.imaps.org/gbc

General Chair
Ted Tessier, ST Assembly Test Services Inc.
480-222-1735
tessiert@statsus.com
Technical Program Co-Chairs
Jon G. Aday, Amkor Technology Inc.
480-821-2408 ext. 5082
jaday@amkor.com
Michael Todd, Henkel Corporation
626-968-6511
Michael.Todd@loctite.com



Message From The Chair

Monday, June 21, 2004

REGISTRATION
11 AM - 5 PM

Professional Development Course (1/2 Day)
Flip Chip Packaging Course - Flip Chip Assembly
1 pm – 5 pm
Instructor: R. Wayne Johnson, Auburn University

Course Description:
Flip chip use is growing in both flip chip-in-package and flip chip-on-laminate applications. This course will provide insight into the design and assembly of electronics using flip chip devices. The practical issues of implementing flip chip technology from wafer bumping to reliability characterization are covered. This course will begin with an examination of bumping options and corresponding design rules. Redistribution will also be discussed. Substrate requirements for flip chip will then be presented including a discussion of high density interconnect options and substrate design. Assembly of flip chip devices adds materials and processes to the standard SMT assembly process and the integration of these into the SMT process flow is examined. Materials and processes to be discussed include lead free alloys, fluxes, underfills (capillary flow, fluxing no-flow, and wafer applied), substrate dehydration, flux and underfill application, underfill curing, inspection, and underfill characterization techniques. The presentation will conclude with a discussion of flip chip assembly reliability testing, test vehicle design and failure analysis.

Lecture Syllabus:

1. Introduction to Flip Chip
2. Flip Chip Bumping
3. Substrates and Substrate Design
4. Assembly
- a. Flux Application
- b. Placement
- c. Reflow
5. Underfill
- a. Capillary
- b. Fluxing
i. Placement Optimization
- c. Wafer Applied
- d. Transfer Molded
6. Reliability and Failure Analysis

Who should attend?
This Workshop is intended for those individuals soon to be responsible for implementing flip chip assembly, suppliers of materials and equipment for flip chip assembly and others interested in flip chip implementation.

The Instructor:
Dr. Wayne Johnson is a Professor of Electrical Engineering at Auburn University and Director of the Laboratory for Electronics Assembly and Packaging (LEAP). At Auburn, he has established teaching and research laboratories for advanced packaging and electronics assembly. Research efforts are focused on materials, processing, and reliability for advanced SMT, wire bond and flip chip assembly. He has published and presented numerous papers at workshops and conferences and in technical journals on flip chip assembly. He received the 1997 Auburn Alumni Engineering Council Senior Faculty Research Award for his work in electronics packaging and assembly.

Dr. Johnson is currently the Technical Vice President of the International Microelectronics and Packaging Society. He was the 1991 President of the International Society for Hybrid Microelectronics (ISHM). He received the 1993 John A. Wagnon, Jr. Technical Achievement Award from ISHM, was named a Fellow of the Society in 1994 and received the Daniel C. Hughes Memorial Award in 1997. He is also a member SMTA and IPC and a Fellow of IEEE.

Dr. Johnson received the B.E. and M.Sc. degrees in 1979 and 1982 from Vanderbilt University, Nashville, TN, and the Ph.D. degree in 1987 from Auburn University, Auburn, AL, all in electrical engineering. He has worked in the microelectronics industry for DuPont, Eaton, and Amperex.


Networking Reception: 6:30 pm
Sponsored by the Global Business Council (OPEN TO ALL REGISTERED ATTENDEES)


Tuesday, June 22

Registration Open: 7 am – 8 pm

Breakfast: 7 am – 8 am

Exhibit Open: 10 am – 8 pm

Welcome Reception in the Exhibit Hall: 6 pm - 8 pm

SESSION 1: FLIP CHIP CHARACTERIZATION AND MODELING
8 am - Noon
CHAIRS: P. HO, UNIVERSITY OF TEXAS - AUSTIN; P. ELENIUS, E&G TECHNOLOGY PARTNERS, LLC

Substrate Electrical Design for 40x40 mm Flip Chip BGA with 125 Gb/s Aggregate Signaling Bandwidth
Alfredo Moncayo, Infineon Technologies

Verification of Submodeling Technique in Thermomechanical Reliability Assessment of Flip-Chip BGA
Yi-Shao Lai, Tong Hong Wang, Advanced Semiconductor Engineering, Inc.

Short Time Thermal Mechanical Shock Wave Propagation in Flip Chip Configuration
Mahavir Nagaraj, C. Steve Suh, Texas A&M University

Transient Deformation and Fracturing of Solder Joints Subjected to Impact Loads
Chang-Lin Yeh, Yi-Shao Lai, Ping-Fong Yang, Advanced Semiconductor Engineering, Inc.

BREAK: 10 AM – 10:30 AM

Full-Wave Solver of Multi-Via Scattering and Microstrip Line Coupling in PCBs
Xiaoxiong Gu, Leung Tsang, Qin Li, Chong-Jin Ong, University of Washington; Kim Lun Lai, City University of Hong Kong; Chien-Min Lin, Taiwan Semiconductor Manufacturing Co., Ltd.; Houfei Chen, Micron; Chung-Chi Huang, Intel

Thermal Interface Material (TIM) Design Guidance for Flip Chip BGA Package Thermal Performance
T. D. Yuan, Hsin-yu Pan, Taiwan Semiconductor Manufacturing Company, Ltd.; Yuan Li, Altera Corporation

Reliability Study for Cu/Black Diamond Structures in Flip-Chip Packaging
Guotao Wang, Paul S. Ho, The University of Texas at Austin; Steven Groothuis, Micron Technology Texas LLC

LUNCH: NOON – 1 PM

SESSION 2: ADVANCES IN BUMPING PROCESS TECHNOLOGIES
1 pm - 5 pm
CHAIRS: H. FUERHAUPTER, ATOTECH USA; K. O’DONNELL, NEXX SYSTEMS INC.

C4 Solder Bump UBM Reliability and Outlook
Jianxing Li, Mahalingam Sankararaman, Raymond Carey, Avi Fuerst, William Johannes, Intel Corporation

Characterization of Reaction Rates and Intermetallic Phase Formation for Cu, Ni and NiV UBM Layers with SnPb and Lead-Free SnAg Solders
K. O’Donnell, NEXX Systems Inc.; D. Gupta, APSTL; P. Silberud, Semitool; C. Lopper, M. Topper, Fraunhofer (IZM)

Enhanced WLP Reliability using Positive Photosensitive Polybenzoxazoles as Interlayer Dielectrics
Ken Imamura, Takashi Hirano, Shusaku Okamyo, Sumitomo Bakelite Co., Ltd.

BREAK: 2:30 – 3 PM

Modulating Characteristics of Bumping Pastes with Analysis of Effects
Bryce Watson, Kester

High Speed Through-mask Copper Electrodeposition for Bumping Process
Zhenqiu Liu, Bill (Qunwei) Wu, Arthur Keigler, John Harrell, NEXX Systems

Low Cost Wafer Bumping for Power Electronics Device Interconnection
Thorsten Teutsch, E. Zakel, PacTech USA - Packaging Technologies, Inc.; T. Oppert, PacTech GmbH; Mervi Paulasto-Kröckel, Motorola GmbH

Evaluation of LCHR: An Electroless Plated Column Bump Technology for Sub 100 um and WLP Applications
D. Gupta, F. Kalle, M. Fria, APSTL

SESSION 3: POSTER - INFRASTRUCTURE FOR FLIP CHIP DEPLOYMENT
6 pm - 8 pm
CHAIR: R. WAYNE JOHNSON, AUBURN UNIVERSITY

Cost-Effective Flip Chip Packaging for Mid-Range Applications
T. G. Tessier, J. Ling, R. Emigh, ST Assembly Test Services Inc.; S. Alvarez, I. K. Shim, T. Wang, ST Assembly Test Services Ltd.

Equipment Advances in Microelectronic Packaging and Assembly
T. Garvin, Panasonic Microelectronics Engineering

A Novel No Flux Wafer Level Solder Reflow
J. Zhang, C. Lee, SEMIgear, Inc.

Advanced Wafer-Level Cleaning for Advanced WLP and Flip Chip
Diane Scheele, Donn Detzler, Dynaloy, Inc.; T. Goodman, Peter Elenius, E&G Technology Partners, LLC

A New, Thick, High Aspect Ratio Plating Resist
Donald W. Johnson, William D. Weber, Harris Miller, Pamela J. Waterson, MicroChem Corp.;
Satoshi Mori, Nao Honda, Nippon Kayaku Co., Ltd.

Reliability Impact of Substrate and Bump Selection for a FC BGA Package
Diane E. Hodges Popps, Thomas H. Koschmieder, Andrew J. Mawer, Freescale Semiconductor

Assembly Process and Package Design for High Performance Flip Chip Applications
Jon G. Aday, Danny T. Brady, Amkor Technology Inc.

Patternable Silicones for Next Generation Packaging Reliability Requirements
Michael E. Kunselman, Lyndon Larson, Brian Harkness, Geoff Gardner, James Alger, Michelle Cummings, Herman Meynen, Dow Corning Corporation.; Mario Gonzalez, Bart Vandevelde, Mathieu Vanden Bulcke, Chistophe Winters, Eric Beyne, IMEC


Wednesday, June 23

REGISTRATION OPEN: 7 AM – 6 PM

SESSION 4: FLIP CHIP ASSEMBLY
8 am - 11:30 am
CHAIRS: D. K. NUMAKURA, DKN RESEARCH; T. G. TESSIER, ST ASSEMBLY TEST SERVICES INC.

A Novel Method of Image Sensor Packaging using Flex-on-Glass Substrate
T. T. Tan, J. H. Burns, A. Chaudhuri, B. H. Pan, C. K. Nah, K. C. Teo, D. Ihms, W. Bauson, S. Fox, T. Garner, Delphi Electronics & Safety; J. R. Troxell, Delphi Research Lab.

Jetting Dispensing of Fluxes for Flip Chip Attachment and Measurement Methods for Ensuring Consistent Flux Coatings
Steven J. Adamson, Asymtek; Stephen Heveron-Smith, Lumetrics

Flip-Chip Bonding for Flexible Circuit Device with Biomedical Application
Daniel N. Pascual, SUSS MicroTec; Steve Callender, Duke University

BREAK: 9:30 AM – 10 AM

Gold to Gold Flip Chip Interconnect using Ultrasonic Bonding for Wafer Level Packaging
Philip Couts, TDK Corporation of America; Ed Onda, SAWTEK Inc.

Thin Substrate Flip Chip Assembly Challenges
Shichun Qu, Daniel J. Foster, Donald R. Banks, Robin E. Gorrell, 3M

Micro Bump Array Construction on the Organic Substrates by Electrical Forming
Masahiro Mizoguchi, Asahi Denka Kenkyusho; Dominique Numakura, DKN Research

LUNCH: NOON – 1 PM


SESSION 5: UNDERFILL RELATED DEVELOPMENTS
1 pm - 4:30 pm
CHAIRS: M. TODD, HENKEL LOCTITE ELECTRONIC MATERIALS; D. PEARD, NATIONAL STARCH & SEMICONDUCTOR

Thermo-Mechanical Properties and Reliability Performance of an Underfill Encapsulant for Flip Chip on Laminate (FCOL) and Flip Chip in Package (FCIP) Applications
Kalyan Ghosh, Mark McCabe, Lord Corporation; Guoyun Tian, Auburn University

Development of Capillary Underfill for Lead-free Packages
Katsushi Yamashita, Yushi Sakamoto, Masahiro Wada, Masahiro Kitamura, Sumitomo Bakelite Co., Ltd.

The Effect of Underfill Materials on Pb-Free Flip Chip Package Reliability
Tie Wang, Jamin Ling, Ming Ying, T. Tessier, IK Shim, ST Assembly Test Services Ltd.

BREAK: 2:30 – 3 PM

Effects of Substrate Design on Underfill Voiding using the Low Cost, High Throughput Flip Chip Assembly Process and No-Flow Underfill Materials
Daniel F. Baldwin, Engent, Inc.; David Milner, Chetan Paydenkar, Georgia Institute of Technology

Enhancing Pb-free Package Performance through Flux-Underfill Synergy
Fritz Byle, Kester

Double Bump Flip Chip
R. Wayne Johnson, Wei Yan, Auburn University; Russell Stapleton, Melissa Kern, Lord Corporation

RECEPTION: 4:30 PM – 5:30 PM


Thursday, June 24

REGISTRATION OPEN: 7 AM - 4:15 PM

SESSION 6: FLIP CHIP TEST AND RELIABILITY
8 am - 11 am
CHAIRS: G. RINNE, UNITIVE ELECTRONICS; D. E. HODGES POPPS, FREESCALE SEMICONDUCTOR

A KGD Enabler: Full Wafer Contact Technology
Tim Pham, John Pitts, Freescale Semiconductor

Study of Electromigration Damage Evolution in High Lead Solders by Wheatstone Bridge Method
Min Ding, Guotao Wang, Paul S. Ho, University of Texas at Austin; Van Pham, Amit Marathe, Raj Master, Advanced Micro Devices

High Currents in WLCSP: Controlling Electromigration
Glenn A. Rinne, Unitive Electronics, Inc.

BREAK: 9:30 AM – 10 AM

Reliability Capability of Reduced Bump Pitch on Flip Chip CBGA and PBGA Packages
Diane E. Hodges Popps, Brett Wilkerson, James Guajardo, Freescale Semiconductor

Studies of Lead-free Flip-chips with a Focus on Enhancing Thermal Fatigue Lives and an Insight into Low-K Delamination
Yi-Shao Lai, Yi-Hsien Lin, Chin-Li Kao, Tong Hong Wang, Advanced Semiconductor Engineering, Inc.

LUNCH: 11:15 AM – 12:15 PM

SESSION 7: PB-FREE AND LOW K FLIP CHIP CHALLENGES
12:30 pm - 4 pm
CHAIRS: J. ADAY, AMKOR TECHNOLOGY, INC.; A. STRANDJORD, IC INTERCONNECT

Design Guidance for the Mechanical Reliability of Low-K Flip Chip BGA Package
Kuo-Chin Chang, Chung-Yi Lin, Mirng-Ji Lii, Taiwan Semiconductor Manufacturing Company, Ltd.; Yuan Li, Altera Corporation

Stress Reduction in Copper - Low K FlipChip Packaging for Reliability Enhancement
Leo M. Higgins III, ASAT, Inc.

Substrate and Underfill Impact on Cu/Low-k Devices: Modeling and Reliability results for Flip Chip BGA Packages
Brett Wilkerson, Jie-Hua Zhao, Diane Hodges Popps, Freescale Semiconductor

BREAK: 2 PM – 2:30 PM

Qualification of Lead Free Flip Chip in Package for High Frequency Applications
Daniel F. Baldwin, Engent, Inc.

Low K and PB-Free Mechanical Durability including Impact on Back-end Assembly, Reliability and Process Control
Terence Q. Collier, CVInc.

Mass Production Experience of Lead Free Sn-Ag Alloy Bump by Electroplating Method
Masakazu Inagaki, Kouichi Kanai, Casio Micronics Co., Ltd.; Kiyotaka Tsuzi, Ishihara Chemical Co., Ltd.

CONCLUDING REMARKS: 4:10 PM

 




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IMAPS-International Microelectronics And Packaging Society and The Microelectronics Foundation
611 2nd Street, N.E., Washington, D.C. 20002
Phone: 202-548-4001

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