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IMAPS Topical Workshop and Exhibition on
Flip Chip Technologies
download pdf of program

Austin Marriott at the Capitol
Austin, Texas 78701
June 20 - 23, 2005

Early Registration Discounts and Hotel Cutoff May 27, 2005

Sponsored by: International Microelectronics And Packaging Society (IMAPS)
Everything in electronics between the chip and the system!

General Chair:
Andrew J.G. Strandjord, FlipChip International
P: 602-431-4728
andrew.strandjord@flipchip.com

Technical Program Co-Chairs:
Jon G. Aday, Amkor Technology Inc.
P: 480-821-2408, ext. 5082
jaday@amkor.com

Theodore G. Tessier, STATS ChipPAC, Inc.
P: 480-222-1735
ted.tessier@statschippac.com


Monday: PDC1 (Flip Chip & CSP) | PDC2 ( Into to Micro Packaging)
Tuesday: Exhibition | Sess 1 (Plenary Marketing) | Sess 2 (Fabrication Processes & System Integration)
Wednesday: Sess 3 (Gold Bumping Tech) | Sess 4 (New Developments in Lead Free Solders)
Thursday: Sess 5 (Reliability - Design, Testing & Modeling) | Sess 6 (Under Fill Materials & Processes)


Monday, June 20, 2005

Registration Hours: 11:30 am – 5 pm

Professional Development Course (1/2 Day) – PDC1
Flip Chip and CSP Technologies – Constructions, Materials, Assembly and Reliability
1 pm – 5 pm
Instructor: R. Wayne Johnson, Auburn University

Course Description:
Flip chip use is growing in both flip chip-in-package and flip chip-on-laminate applications. This course will provide insight into the design and assembly of electronics using flip chip devices. The practical issues of implementing flip chip technology from wafer bumping to reliability characterization are covered. This course will begin with an examination of bumping options and corresponding design rules. Redistribution will also be discussed. Substrate requirements for flip chip will then be presented including a discussion of high density interconnect options and substrate design. Assembly of flip chip devices adds materials and processes to the standard SMT assembly process and the integration of these into the SMT process flow is examined. Materials and processes to be discussed include lead free alloys, fluxes, underfills (capillary flow, fluxing no-flow, and wafer applied), substrate dehydration, flux and underfill application, underfill curing, inspection, and underfill characterization techniques. The presentation will conclude with a discussion of flip chip assembly reliability testing, test vehicle design and failure analysis.

Lecture Syllabus:

1. Introduction to Flip Chip
2. Flip Chip Bumping
3. Substrates and Substrate Design
4. Assembly
a. Flux Application
b. Placement
c. Reflow
5. Underfill
a. Capillary
b. Fluxing
i. Placement Optimization
c. Wafer Applied
d. Transfer Molded
6. Reliability and Failure Analysis

Who should attend?
This Workshop is intended for those individuals soon to be responsible for implementing flip chip assembly, suppliers of materials and equipment for flip chip assembly and others interested in flip chip implementation.

The Instructor:
Dr. Wayne Johnson is a Professor of Electrical Engineering at Auburn University and Director of the Laboratory for Electronics Assembly and Packaging (LEAP). At Auburn, he has established teaching and research laboratories for advanced packaging and electronics assembly. Research efforts are focused on materials, processing, and reliability for advanced SMT, wire bond and flip chip assembly. He has published and presented numerous papers at workshops and conferences and in technical journals on flip chip assembly. He received the 1997 Auburn Alumni Engineering Council Senior Faculty Research Award for his work in electronics packaging and assembly.

Dr. Johnson is currently the Technical Vice President of the International Microelectronics and Packaging Society. He was the 1991 President of the International Society for Hybrid Microelectronics (ISHM). He received the 1993 John A. Wagnon, Jr. Technical Achievement Award from ISHM, was named a Fellow of the Society in 1994 and received the Daniel C. Hughes Memorial Award in 1997. He is also a member SMTA and IPC and a Fellow of IEEE.

Dr. Johnson received the B.E. and M.Sc. degrees in 1979 and 1982 from Vanderbilt University, Nashville, TN, and the Ph.D. degree in 1987 from Auburn University, Auburn, AL, all in electrical engineering. He has worked in the microelectronics industry for DuPont, Eaton, and Amperex.

Professional Development Course (1/2 Day) – PDC2
Introduction to Microelectronics Packaging Technology
1 pm – 5 pm
Instructor: Phil Creter, Creter & Associates

Course Description:
This course will provide an introduction to microelectronics packaging technology for engineers, technicians and others involved in manufacturing, processing, development, quality, sales and marketing. Emphasis will be on visual aids including actual samples and a variety of photos and figures to provide the attendee with not only a solid base in how various microcircuits are made by various materials, processes and equipment but also what they look like. The attendee will learn classic hybrid definitions as well as current state of the art terminology of materials, processes and equipment, including: thick film technology, thin film technology and monolithic semiconductor technology; substrates (ceramic, conductors, dielectrics, co-fired, LTCC); components (passives, actives, chips vs. discrete, SMT components and flip chip); assembly including details of die attach, wire bonding and micro soldering, rework & repair; final assembly including details of visual inspection techniques, test, and failure analysis. Also covered is design, documentation standards, acronyms, list of symbols, clean rooms and handling techniques. Video clips highlight various microcircuit assembly processes. Included in the course handout is an updated glossary and list of references the attendee will find invaluable.

Who should attend?
This course is designed for the attendee who has little initial familiarity with Microelectronics Packaging engineering terminology but would like to relate it to real life, everyday applications. Ideal for, entry level technicians and engineers but also for people in quality assurance, sales, marketing, purchasing, safety, administration and program management. Emphasis will be on visual aids.

The Instructor:
Phil Creter is a long-time member of IMAPS, having joined the New England Chapter of ISHM in 1974. He is a Fellow of the Society, and has been elected National Treasurer and President of the New England Chapter (twice). He received a BS in Chemistry from Suffolk University and has published numerous papers, holds a U.S. patent, has made many technical presentations (received Best Paper of Session award IMAPS 1998) and has chaired several technical sessions. He is currently a consultant (Creter & Associates) and has over 30 years of microelectronics packaging experience at Polymer Flip Chip Corporation, Mini-Systems, GTE and Itek Corporation. His past positions include GTE Microelectronics Center Manager, Process Engineering Manager, Process Development Manager, Materials Engineering Manager and Manufacturing Engineer. He currently teaches professional development courses at microelectronics events and is a certified instructor for the Department of Homeland Security.


Tuesday, June 21

Registration Hours: 8 am – 6:30 pm

Exhibit Hours: 10 am – 6:30 pm

Welcome Reception in the Exhibit Hall: 5 pm – 6:30 pm

Session 1: Plenary Marketing
8:30 am – 11:30 am
Chair: Andrew J.G. Strandjord, FlipChip International

Market Expectations for Flip Chip and Wafer Level Packages: High Growth Prospects
E. Jan Vardaman, TechSearch International, Inc.

Emerging Wafer Level Technologies, Looking Beyond WLCSPs
Ted Tessier, STATSChipPAC Inc.

Alpha Particle Concerns in Wafer Level Packages
Glenn A. Rinne, P. Chilikuri, Unitive Electronics, Inc.

Break in Exhibit Hall: 10 am – 10:30 am

The Worldwide IC Packaging Market
Sandra Winkler, Electronic Trend Publications

Tensile Deformation of WLCSP and Flip Chip Solder Joints
Robert Darveaux, Amkor Technology / Arizona State University - East

Lunch in Exhibit Hall: Noon – 1 pm

Session 2: Fabrication Processes and Systems Integration
1 pm – 4:30 pm
Chairs: Thorsten Teutsch, PacTech USA - Packaging Technologies, Inc.; Haluk Balkan, FlipChip International, LLC

Design Guidelines for Fine Pitch Flip Chip Production
Haluk Balkan, Jacinta Aman Lim, Dan Berry, Guy Burgess, FlipChip International, LLC

Lead Free SiP Wireless Modules Fabricated with Flip Chips on Silicon Integrated Passive Device Substrate
Yinon Degani, SyChip Inc.

Chemical Resistance of Polyimide Passivations in Wafer-Level Photoresist Stripping Processes
Raymond Chan, Diane Scheele, Dynaloy, LLC; Thomas Goodman, E&G Technical Partners

Break in Exhibit Hall: 2:30 – 3 pm

Fine Pitch Solder Stencil Printing using Low Cost Electroless Ni/Au UBM for Memory Devices
Thorsten Teutsch, A. Scheffler, E. Zakel, PacTech USA - Packaging Technologies, Inc.; Carlo Gamboa, Bo Chang, Cypress Semiconductor

Standards for the Procurement and use of Die Devices
Mike Roughton, Donald Radley, Ken Ball, Alun Jones, MGR Consultants/ENCAST

C4NP: New Solder Bumping Technology - Low Cost & Lead Free
Klaus Ruhmer, SUSS MicroTec, Inc.; Dietrich Toennies, SUSS MicroTec – Germany; Emmett Hughlett, Peter Gruber, IBM TJ Watson Research Center; Patrick O'Leary, IBM Microelectronics Division

Welcome Reception in the Exhibit Hall: 5 pm – 6:30 pm

Wednesday, June 22

Registration Hours: 7:30 am – 4:30 pm

Session 3: Gold Bumping Technologies
8 am – 11:30 am
Chairs: Daniel D. Evans, Jr. Palomar Technologies Inc.; Jamin Ling, Kulicke & Soffa Industries Inc.

Flip Chip Type Camera Module Package for Mobile Phones with Low Cost Electro-Less Nickel/Gold Bump
J. K. Lyu, J.-D. Kim, Samsung Techwin Co., Ltd.

An Innovative Approach to Low Cost, High Performance, Lead-Free DCA
Elwyn Wakefield, Micro-Design; George A. Riley, FlipChips Dot Com

Low Profile Flat Top Ball Bumps for Next Generation 1st Level Interconnect
Daniel D. Evans, Jr., Palomar Technologies, Inc.

Break: 9:30 am – 10 am

Gold Bump Formation by High Speed Noncyanide Gold Electroplating
Bill Wu, Zhen Liu, Arthur Keigler, NEXX Systems

The Theken Disc - A Medical Marvel Description of the Theken Disc as Manufactured by Valtronic USA, Inc.
Donald Styblo, Valtronic USA; Rich Remer, Theken Disc

Stud Bumping – An Alternative Bumping Strategy
Jamin Ling, Matt Meyer, Matt Osborne, Vincent McTaggart, Kulicke & Soffa Industries Inc.

Lunch: 11:30 am – 12:30 pm

Session 4: New Developments in Lead Free Solders
1 pm – 4:30 pm
Chairs: Glenn A. Rinne, Unitive Electronics, Inc.; Robert Darveaux, Amkor Technology

Local Creep and Fatigue in SnAg3.8Cu0.7 Solder
Pascal P. Jud, Guenter Grossmann, Urs Sennhauser, EMPA

Electroplating Tin-Silver Solder Bumps for Wafer Level Packaging
Jim (Zhongqin) Zhang, Zhen Liu, Arthur Keigler, NEXX Systems

Development of Lead-Free Flip Chip Packages with Sn-Cu Bumps
Don Son Jiang, L. J. Chen, Y. P. Wang, C. S. Hsiao, Siliconware Precision Industries Co., Ltd.

Break: 2:30 pm – 3 pm

Total Packaging Solution for Low K Device/Pd Free Bump
Mitsuo Sugino, Sumitomo Bakelite Co., Ltd.

Electrodeposition of Eutectic Gold-Tin Alloy for Microelectronic Applications
George Hradil, Edward Hradil, Hana Hradil, Technic Inc.

Tin Pest in Pb-Free Solders
Glenn A. Rinne, Unitive Electronics, Inc.


Thursday, June 23

Registration Hours: 7:30 am – 3:30 pm

Session 5: Reliability (Design, Testing, and Modeling)
8 am – 11:30 am
Chairs: Daniel F. Baldwin, Engent Inc.; Theodore G. Tessier, STATSChipPAC Inc.

Thermal Design for Power CSP Packages
Dennis Lang, Fairchild Semiconductor

Land Grid Array (LGA) as a Pb-Free Approach for Ceramic Ball Grid Array Packages
Joachim Rayos, Linda Bal, Thomas Koschmieder, Terry Burnette, Freescale Semiconductor, Inc.

Intermetallic Compound Formation in Flip Chip Solder Bump and Its Impact to Product Reliability
Hong Yang, Joe Patterson, Francois Guindon, Applied Micro Circuits Corporation

Break: 9:30 am – 10 am

Thermo-Mechanical Modeling for DOE Analysis of Over-Molded Flip-Chip Packages
Yu Gu, Mohsen Haji-Rahim, Daniel Jin, RF Micro Devices

FlipChip BGA Bump & Board Level Reliability: Power & Thermal Cycling Compared
Abu Eghan, Hoa Do, Leilei Zheng, Lan Hoang, Stephen Pan, Xilinx Inc.

In Situ Stress Analysis and Reliability Assessment of Flip Chip on Organic Board using Power Cycling Techniques
Daniel F. Baldwin, Engent, Inc.; Jian Zhang, GE Global Research

Lunch: 11:30 am – 12:30 pm

Session 6: Under Fill Materials and Processes
1 pm – 3:30 pm
Chairs: Guy Burgess, Flip Chip International, LLC; R. Wayne Johnson, Auburn University

Plasma Treatment of Pre-Underfill Flip Chip Devices
Jack Zhao, March Plasma Systems

Near Void Free Hybrid No-Flow Underfill Flip Chip Process Technology
Daniel F. Baldwin, Engent, Inc.; Michael Colella, Intel Corp.

Assembly and Reliability of Lead-free Flip Chip Devices with a Nanofilled No-flow Underfill Material
Ananth Prabhakumar, Donald Buckley, Arun Chaudhuri, Frank Stepniak, Paul Gillespie, Ryan Mills, Slawomir Rubinsztajn, Sandeep Tonapi, General Electric Global Research Center

Low Void Solder Paste for Flip Chip Applications
Guy Burgess, Joan K. Vrtis, FlipChip International, LLC

Flux Compatibility Study on Flip Chip Underfills
Renzhe Zhao, Qing Ji, George Carson, Michael Todd, Gary Shi, Henkel Corporation

Concluding Remarks: 3:30 pm


Housing (Hotel Cut-off is May 27, 2005)

Housing Accommodations must be made directly to:

Austin Marriott at the Capitol
701 East 11th Street
Austin, TX 78701
P: 512-478-1111 or 800-648-4462

Single/Double: $159
Please reference IMAPS when making reservations.

Austin Marriott requires a deposit for the first night's room and tax to hold your room. Deposit refunded if reservation is cancelled fourteen (14) days prior to arrival.


 



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IMAPS-International Microelectronics And Packaging Society and The Microelectronics Foundation
611 2nd Street, N.E., Washington, D.C. 20002
Phone: 202-548-4001

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