The International Microelectronics Assembly and Packaging Society (IMAPS) is organizing an Advanced Technology Workshop and Tabletop Exhibition on “Packaging the Next Generation of Nano Devices” to be held April 30 and May 1 in Albany, New York.
Overview: With each new generation of high density devices, the packaging community faces ever more difficult challenges. Diverse technologies such as: 3D, 2.5D, silicon carrier, MEMs, Hybrid electro-opto packages, etc require different packaging technologies, different materials, different processing, testing etc. All these variables are the focus of this conference which will be held in the heart of New York State's premier silicon device fabrication center. We hope that you will come and join us to see the progress of the industry and see where it is headed.
Tuesday, April 30, 2013
CNSE Site/Lab Tours: 10:00 am– 12:00 pm
Registration: 12:00 pm – 7:00 pm
Tabletop Exhibition: 3:00 pm - 7:00 pm
Opening Remarks: 12:30 pm – 12:45 pm
Ray Fillion, General Chair
Keynote Presentation: 12:45 pm – 1:30 pm
College of Nanoscience and Engineering Overview and Derivative Center
With over $14 billion in high-tech investments, the College of Nanoscale Science and Engineering (CNSE) represents the world’s most advanced university-driven research enterprise, with over 300 corporate partners. CNSE’s Albany Nanotech Complex contains 135,000 square feet of Class 1 capable cleanrooms, including a fully-integrated, 300mm wafer, computer chip pilot prototyping and demonstration line, as well as a new expansion that houses the world’s first Global 450mm Wafer Consortium (G450C).
CNSE’s Derivative Center offers a fully integrated 65nm low power CMOS with plans for 28nm LP BEOL process flows, derivative development in areas that include silicon photonics, memory, and 3D integration. These technologies are fully installed and are available for fully integrated customer prototypes.
In this talk, an overview of CNSE and these leading edge technologies will be discussed.
Dr. Douglas Coolbaugh, Derivatives and 3Di Manager
College of Nanoscale Science and Engineering at Albany-State University of New York NanoFab
Douglas Coolbaugh received his PhD in Physical Chemistry from SUNY Binghamton, NY in 1987. Doug retired from IBM in 2010 after working 30 years in microelectronics development. Presently he is the Assistant VP of derivatives at the College of Nanoscale Science and Engineering.
SESSION I: Advanced Processing & Reliability
Chair: Benson Chan, Endicott Interconnect
1:30 pm - 5:30 pm
Waferbumping Fluxes Enabling 2.5D and 3D Technology
Andy Mackie, Indium Corporation (Maria Durham, Indium Corporation; Laura Mauer, SSEC)
Wedge Bonding New Wire Alloys for Nano Applications
Lee Levine, Hesse Mechatronics Inc. (Joseph Bubel)
Solder Joint Encapsulant Adhesive - POP TMV High Reliability And Low Cost Assembly Solution
Wusheng Yin, YINCAE Advanced Materials, LLC (Mary Liu)
Inspection and Metrology for 2.5/3D Interconnect Solution
Victor Vartanian, SEMATECH, 3D Interconnect Division
Break in Exhibit Hall:3:30 pm - 4:00 pm
Chemically Vapor Deposited Polymer Coatings for the Environmental Protection of Micro- and Nano-Electronics
Seth Johnson, GVD Corporation
Understanding Temperature Programmable Behavior of SWCNT-Epoxy Undefill for Component Level Reworkability
Vishwas Bedekar, University of Arkansas (Ajay Malshe, University of Arkansas; Deepnarayan Gupta, Hypres Inc)
Reliability of Lead-Free BiAgX Solder Paste for Die Attach application
Hongwen Zhang, Indium Corporation (Runsheng Mao, Ning-Cheng Lee)
Reception in Exhibit Hall: 5:30 pm - 7:00 pm
Wednesday, May 1, 2013
Registration Open : 7:00 am - 4:00 pm
Tabletop Exhibits : 10:00 am - 3:30 pm
Opening Remarks: 8:00 am – 8:15 am
John Torok and Jing Zhang, Technical Co-Chairs
Keynote Presentation: 8:15 am – 9:00 am
Advancing Technology in Expert Integrated Systems
In the era of smart computing, big data and deep analytics place a strong demand on our IT infrastructure and are significant drivers for hardware development to meet those needs. The computing systems on which these applications can efficiently operate are integrated systems where computing, storage, networking and software components work well together. High compute density, high bandwidth and low-latency are key metrics to define the raw processing capability of these systems that provide a foundation for the targeted applications. These key metrics must be met under stringent power and cost constraints. New technology elements including nanotechnology provide many opportunities. Some examples are 3D stacked silicon and packaging provides computing density, integrating new magnetic material enables advanced voltage regulation integrated into devices, materials with advanced propagation characteristics overcome signal loss limitations, and advances in thermal interface materials allow the increased performance to be realized while the cost, power and reliability constraints are still met.
Dr. W. Dale Becker, Distinguished Engineer
Dale Becker received the B.E.E degree from the University of Minnesota, M.S.E.E. from Syracuse University and the Ph.D. from the University of Illinois at Urbana Champaign. He is a Distinguished Engineer in IBM Systems and Technology Group and a member of the IBM Academy of Technology. He is the System Electrical Architect for the IBM POWER and System Z Enterprise Systems. His responsibilities include designing the high-speed channels to enable the computer system performance and the power distribution networks for reliable operation of the integrated circuits that make up the processor subsystem. Dr. Becker has 25 patents on electrical design of computer systems and has presented 75 papers in refereed journals and international conferences covering many aspects of electrical computer system design including power distribution analysis and design and modeling of signal and power distribution networks. He is a senior member of IEEE, a iNEMI Technical Committee member and a member of IMAPS.
SESSION II: 3D Processing
Chair: Ray Fillion, Fillion Consulting
9:00 AM – 10:30 AM
Packaging Materials for 2.5/3D Technology
Tony Ruscigno, NamicsTechnologies, Inc. (Brian Schmaltz).
A Novel Underfill for 3D TSV Package
Wusheng Yin, YINCAE Advanced Materials, LLC
Characterization of AL-X Carbon Resistors
George Hernandez, Auburn University (Stephen Patenaude, Daniel Martinez, Maria Auad, Michael Hamilton)
Break in Exhibit Hall:10:30 am - 11:00 am
SESSION III: 3D Interconnects
Chair: Ying Yu, IBM Corporation
11:00 am - 12:30 pm
3D Integration with High Performance Coaxial Through Silicon Via (TSV)
Stephen Adamshick, College of Nanoscale Science and Engineering, University at Albany, SUNY (Douglas Coolbaugh, Michael Liehr)
Development of Glass and Silicon 3D-IC Interposers: A Comparison in Performance and Reliability
Aric Shorey, Corning Incorporated
Standard Measurement Methods for Enabling 3D Stacked Integrated Circuits
Richard Allen, SEMATECH (Victor Vartanian, Iqbal Ali, SEMATECH; David Read, NIST/SEMATECH)
Lunch in Exhibit Hall: 12:30 pm - 1:30 pm
SESSION IV: 3D Advanced Packaging & Materials
Chairs: John Torok, Jing Zhang, IBM Corporation
1:30 pm - 4:00 pm
Infusion of Next Generation of Nano Devices into Military/Space Standards
Shri Agarwal, NASA Jet Propulsion Laboratory - Will be presented by Committee
Signal Integrity Comparison between Copper and CNT-based TSVs
Bruce Kim, City University of New York (Sukeshwar Kannan, Anurag Gupta, Kaushal Kannan)
Break in Exhibit Hall: 2:30 pm – 3:00 pm
Ink-jet Printed Cu/Ag Memristor
Simin Zou, Auburn University (Pingye Xu, Michael Hamilton)
Organic Interposer Technology for 2.5D and 3D Packages
Tomoyuki Yamada, Kyocera America, Inc.
Closing Remarks - Ray Fillion: 4:00 pm