Program:

4:00   Registration and networking

4:30   Nathan Onbattuvelli, PhD Student from Oregon State University
“Injection Molding of SiC ceramics for Power Electronics.”

Abstract: Silicon carbide (SiC) and aluminum nitride (AlN) have a unique combination of high thermal conductivity, low coefficient of thermal expansion, mechanical strength and chemical inertness. In order to translate these properties into demanding applications in electronic, energy, chemical and transportation sectors, it is necessary to develop net shaping processes that result in fully dense microstructures. The current research aims on fabricating a fully dense power semiconductor packaging based on SiC and AlN. With their properties mentioned above, these ceramics potentially fight the drawbacks of epoxy-based packaging including delamination of substrates and detachment of wire bonds. Powder injection molding (PIM) is chosen over the other fabrication techniques in order to facilitate high volume, cost effective production of complex parts. Rare earth oxides were involved to assist the liquid phase sintering of covalently bonded SiC and AlN. Effect of material (particle size, solids loading) and process parameters (sintering conditions) over the microstructure and thus the properties were studied. Additional efforts were taken to understand the effect of material parameters (particle size, solids loading) over the process parameters (rheology, debinding kinetics and sintering kinetics).

5:00  James Morris, Professor from Portland State University
“Nanopackaging: Nanotechnologies in Microelectronics Packaging."

Abstract: Nanotechnologies offer a variety of materials options for reliability improvements in microelectronics packaging, primarily in the applications of nanoparticle nanocomposites, or in the exploitation of the superior properties of carbon nanotubes. Nanocomposite materials are studied for resistors, high-k dielectrics, electrically conductive adhesives, conductive “inks,” underfill fillers, and solder enhancements, while CNTs may also find thermal, interconnect, and shielding applications. The talk will focus on these technologies, with some discussion of nanoparticle and CNT properties, modeling, and technology scaling, and a mention of the packaging reliability issues for post-CMOS nanoelectronics technologies.

5:30   Roger Devaney, VP - Laboratory Director of Hi-Rel Labs
“The Metallurgy and Failure Analysis of Solder Joints in Electronics.”  

6:00   Vikas Shilimkar, PhD student at Oregon State University
"Impact of Metal Fill on On-Chip Interconnect Performance."

Abstract: Chemical Mechanical Polishing (CMP) employed in advanced IC fabrication processes, dummy metal fill structures are added in the low metal density areas to achieve global uniformity. It is important to study the impact of metal fills on on-chip transmission line structures as these topologies are gaining more importance for longer interconnections in high speed, low power VLSI designs. The addition of floating or grounded metal fills leads to capacitive and inductive parasitic loading of interconnects. This in turn results in impedance mismatches, increased delay, dispersion and increased loss. This paper deals with the analysis of on-chip interconnects considering metal fills. The first contribution of this work is to show the effects of metal fills on transmission line characteristics. We show the change in frequency dependent behavior of characteristic impedance and propagation constant when metal fills are inserted. We further study the impact of metal fill placement, feature size and shape on the transmission line characteristics. We show that for a ~50% metal density, 9?mx9?m metal fill increases the distributed capacitance by ~30% and distributed resistance by ~29%. In comparison, smaller metal fills of 3?mx3?m result in a distributed capacitance increase of ~20% and distributed line resistance increase of ~19% for the same metal density. Octagonal metal fill for the same metal fill area (81?m x 81?m) improves the performance by reducing the capacitive impact to ~26% and loss impact to ~16%. This work concludes with design recommendations for on-chip transmission lines considering metal fills.

6:30  Event Wrap-up (event review, next event, announcements)                      

6:45 Dinner

Registration:

On-line Registration

Registration Closes: 5pm EST on February 8, 2010
Cost:
IMAPS members - $ 20.00 pre-registered ($25 on-site). 
Non-members - $ 30.00 pre-registered ($35 on-site). 
Students with ID – $ 5.00

On-line registration is by credit card only. On-site registration is by cash or check only.

Event Location:

Kyocera Industrial Ceramics
5713 East Fourth Plain Blvd.
Vancouver, WA 98661

On-site POC is Scott Tse at Scott.Tse@kyocera.com