Sheraton Palo Alto Hotel
Palo Alto, California USA
October 19 - 22, 2003

General Chair:
Sarosh Patel
Sarosh.patel@stanfordalumni.org

Technical Program Chair:
Ray Alexander, NCR Systems Engineering
ra121971@ncr.com

Sunday, October 19

Registration: 6 pm - 8 pm

Reception: 7 pm - 8 pm

Monday, October 20

Registration: 7:30 am - 4:30 pm

Continental Breakfast: 8 am - 9:15 am

Opening Remarks: 9:15 am - 9:30 am
Workshop Chairs

Session 1: Interconnect Technologies I - Connectors
Session Chair: Munawar Ahmad, Molex Inc.
9:30 am - Noon

Interconnection Technology for the Next Generation
Roger E. Weiss, Paricon Technologies Corp.

Connector Designs to Meet the Demands of Tomorrow
Adam J. Houston, Molex Inc.

Break: 10:30 am - 11 am

Cable used for Differential Signaling over GHz
Yshihiro Hirakawa, Judd Wire Inc.

Optimized Interconnect Solutions for High-Performance System Data Transmission
Josh Nickel, Andreas Cangellaris, Patrick Codd, Stanford W. Crane, Jr., James Jeon, Zsolt Horvath, Silicon Bandwidth, Inc.

Lunch: Noon - 1 pm

Session 2: Power Components/Subsystems
Session Chair: Herman Chu, Procket Networks Inc.
1 pm - 4:30 pm

Voltage and Geographic Constraints of Power Infrastructure of Telco Products, A Holistic Approach
Mark Imbertson, Procket Networks Inc.

System-in-a-Package Solutions for DC-DC Converters
David Bolognia, Amkor Technology

3-D Power Network Embedded in a High-Speed Cube
Christian M. Val, 3DPlus

Break: 2:30 pm - 3 pm

Advanced DC/DC Converters for Intermediate Voltage Bus Architecture Utilize Land Grid Array Packages
Mikhail Guz, Power-One Inc.

Low Temperature Co-Fired Ceramics on Metal (LTCC-M): An Enabling Technology for RF/Micro Wave High Power SMT Packaging
Edmar Amaya, Joe Mazzochette, Lamina Ceramics Inc.

Reduction of Distributed Power Supply Impedance at High Frequencies using Ultra-thin Substrates as Embedded Capacitors
John Andresakis, Takuya Yamamoto, Nick Biunno, Oak-Mitsui Technologies

Welcome Reception: 5 pm - 5:30 pm
Dinner: 5:30 pm - 7 pm

Tuesday, October 21

Registration: 7:30 am - 4 pm

Continental Breakfast: 7:30am - 8:30 am

Session 3: Interconnect Technologies II - Proudly presents Real Bandwidth
Session Chair: Jeff Cain, Cisco Systems
8:30 am - Noon

Design Considerations for 10Gbit/sec Data Links
Herb Van Deusen, W. L. Gore

AC Coupled Interconnect for High-Density High-Bandwidth Packaging
Paul Franzon, Stephen Mick, John Wilson, Lei Luo, Karthik Chandrasakhar, NC State University

High Speed Differential Transmission Lines
Henning Hansen, LEONI High Speed Cables GmbH

Influence of Multiline Cross Talk on Eye Patterns at High Speed
Henri Merkelo, atSpeed Technologies

Break: 10:30 am - 11 am

4-PAM/20Gbps Transmission over 20-in FR-4 Backplane Channels: Channel Characterization and System Implementation
Youngsik Hur, M. Maeng, S. Chandramouli, F. Bien, E. Gebara, K. Lim, J. Laskar, Georgia Institute of Technology

Designing the 12.5 Gb/s Back-Plane
Bilal Ahmad, Cisco Systems

Lunch: Noon - 1 pm

Session 4: Interconnect Technologies III - Within Package and Package to PWB
Session Chair: Bill Maltz, Electronic Cooling Solutions, Inc.
1 pm - 3:30 pm

Applied FEM Techniques in Ceramic Feedthru Package Design
Mark Eblen, Kyocera America, Inc.

Accurate Extraction of Time Domain Performance through Windowless Transforms
Jayaprakash Balachandran, Arun Chandrasekhar, Eric Beyne, Walter De Raedt, Bart Nauwelaers, IMEC

Fundamental Issues of Particle-in-Elastomer Sockets
Weifeng Liu, Hewlett Packard; Michael Pecht, University of Maryland

Break: 2:30 pm - 3 pm

High Reliability Second Level Interconnects using Polymer Core BGAs
Sashidhar Movva, Ryan Thorpe, Kyocera America, Inc.

Reception: 4 pm - 4:30pm
Dinner: 4:30pm - 6 pm

Wednesday, October 22

Registration: 7:30 am - Noon

Continental Breakfast: 7:30 am - 8:30 am

Session 5: EMI
Session Chair: Ray Alexander, NCR Systems Engineering
8:30 am - Noon

Design-Class Simulation for the EMC Design of Electronics
Fred German, Flomerics Inc.

Mounting of Microelectronic Components at Room Temperature with Solders and Local Heat Sources
Timothy P. Weihs, D. Van Heerden, O.M. Knio, Reactive NanoTechnologies, Inc.

EMI Evaluation of an Interconnect System for Gigabit Applications
Wendemagegnehu Beyene, Hao Shi, Newton Cheng, Chuck Yuan, Rambus Inc.

Low Inductance Thin Film Capacitors for Decoupling Applications
Nobuo Kamehara, John D. Baniecki, Takeshi Shioga, Kazuaki Kurihara, Fujitsu Laboratories Ltd

Break: 10:30 am - 11 am

An Investigation of the Importance of Decoupling Capacitor Values in High-Speed Digital PCBs
Jun Fan, James L. Knighten, NCR; Lin Zhang, Giuseppe Selli, Jingkun Mao, Richard E. DuBroff, James L. Drewniak, University of Missouri-Rolla; Bruce Archambeault, IBM

Integrated Decoupling in High Performance IC Packaging
Leonard W. Schaper, Richard K. Ulrich, University of Arkansas

Concluding Remarks

Register On-Line and $ave

Don't miss out on the Thermal Management 2003 ATW
held in conjuction with this event.

Hotel Information:

Hotel Cut-off is September 12, 2003
Hotel accommodations must be made directly to:

Sheraton Palo Alto Hotel
625 El Camino Real
Palo Alto, CA 94301
Phone: 800-874-3516
Email: SheratonReservation@pahotel.com
When making reservations, please reference IMAPS.

Single/Double: $179

Sheraton Palo Alto Hotel requires a deposit for the first night's room and tax to hold your room. Deposit refunded if reservation is cancelled fourteen (14) days prior to arrival. After which time, deposit is non-refundable.

The Sheraton Palo Alto Hotel is located 400 meters (1/4 mile) from the Palo Alto Caltrain station. Caltrain and connecting shuttle buses provide frequent service to San Jose and San Francisco airports. Downtown Palo Alto, centered on University Avenue, is within easy walking distance. This is an alternate method to car rental for getting around between Bay Area airports and the hotel where the workshop will be held. More detailed step-by-step directions and useful links to the different transit systems will be provided shortly. Please check back soon.

Transportation to/from the Sheraton