Sheraton Palo Alto Hotel
Palo Alto, California USA
October 27 - 29, 2004

(held in conjunction with the ATW on Thermal Management
October 25-27 - Sheraton Palo Alto)

Wednesday, October 27

Registration: 11 am – 4 pm

Session I: Interconnect Technologies I (Cables and Back Planes)
Session Chair: Munawar Ahmad, Molex
1 pm – 4 pm

State of the Art of Electrical High Speed Backplanes
Franz Gisin, Sanmina-SCI

Advancing from Current High Speed Standards to DDR and QDR
Henri Merkelo, atSpeed Technologies

Correlating Passive Interconnect Channel Simulation and Measurement Results at 10Gbps
Eric Montgomery, Northrop Grumman

Break: 2:30 pm – 3 pm

Reducing System Costs while Maintaining Performance by Optimizing the Passive Channel
Chris Heard, Robert Cutler, Teradyne Connection Systems

Evaluating PCB Laminates Relative to Tolerances, their Electrical Values, the Ability to Process, and Transmission Lines Routing Issues Related to Laminate Thickness
Eric Montgomery, Steve Vetter, Northrop Grumman

Reception: 4 pm – 4:30 pm
Dinner: 4:30 pm – 5:30 pm

Thursday, October 28

Registration: 8 am – 4 pm

Continental Breakfast: 8 am – 9 am

Session 2: EMI
Session Chair: Jim Knighten, NCR
9 am – Noon

High Capacitance Density Thin Film Capacitors for Decoupling Applications
Nobuo Kamehara, John D. Baniecki, Takeshi Shioga, Kazuaki Kurihara, Fujitsu Laboratories Ltd.

Effective Low Noise Power Delivery for Susceptible Components on Multi-Layer PCBs by Means of DC-Connected Power Islands
Giuseppe Selli, James L. Drewniak, Richard E. DuBroff, University of Missouri-Rolla; Norman W. Smith, Dean J. McCoy, Jun Fan, James L. Knighten, Teradata, a division of NCR

Streamlining Collaborative Thermal and EMC Design using Analysis-Based, Integrated Virtual Prototyping Tools
Federico Centola, Sherman Ikemoto, Flomerics Inc.

Break: 10:30 am – 11 am

Impact of Embedded Capacitor Materials on Board Level Reliability
William Balliette, Joel Peiffer, 3M Company

EMI Specifics of Low-Voltage Power MOSFETs in Buck Converter Applications
Zhe Li, David Pommerenke, University of Missouri-Rolla; Cheung-Wei Lam, Bob Steinfeld, Apple Computer

Lunch: Noon – 1 pm

Session 3: Interconnect Technologies II (Connectors)
Session Chair: Kim Davies, Sanmina-SCI
1 pm – 3:30 pm

AC Coupled Connectors
Karthik Chandrasekar, John Wilson, Stephen Mick, Paul Franzon, North Carolina State University

An Electrically Invisible Separable Contact Applied to Levels 1-6
Roger E. Weiss, David M. Barnum, Paricon Technologies Corp.; Scott McMorrow, Teraspeed Consulting Group LLC

High Speed Backplane/Mezzanine Interconnects and Decoupling Interposers for Improved Power Delivery
Josh Nickel, Stanford W. Crane, Silicon Bandwidth, Inc.

Break: 2:30 pm – 3 pm

Design of a Broadband Impedance Matching Network for Cable Characterization in High-Speed Digital Signaling
Norman Smith, Shaofeng Luan, Jun Fan, James L. Knighten, Ray Alexander, Teradata, a division of NCR

Reception: 4 pm – 4:30 pm
Dinner: 4:30 pm – 5:30 pm

Friday, October 29

Registration: 8 am – 4 pm

Continental Breakfast: 8 am – 9 am

Session 4: Interconnect Technologies III (Board Level Interconnects - Sockets and Components)
Session Chair: Ray Alexander, NCR
9 am – Noon

Advanced HiCTE Flip Chip on High Performance Laser-Fused Cu/Low-K Telecom Device: a Materials, Process Reliability, and Manufacturing Analysis
Surasit Chungpaiboonpatana, Mindspeed (Conexant) Inc.; Frank G. Shi, University of California – Irvine

Limitations in Ultra High Speed Serial Communications - 20 Gb/s and beyond - Across Common PWB Microstrip Circuits
Joseph (Ted) T. Dibene II, Intel Corporation; Kevin B. Quest, University of California –San Diego; James L. Knighten, Teradata, a division of NCR

High Frequency Copper Migration Phenomena in Stress-Induced Phosphorus Mold Epoxy: an Electrochemical, Materials, and Package Model Analysis
Surasit Chungpaiboonpatana, Mindspeed (Conexant) Inc.; Frank G. Shi, University of California – Irvine

Break: 10:30 am – 11 am

Speedy Delivery Signal Propagation on Dispersive Lossy Transmission Lines
Robert H. Flake, John F. Biskup, The University of Texas at Austin

Shaping Via Structures for Optimum Signal Processing and Signal Routing
Eric Montgomery, Northrop Grumman

Lunch: Noon – 1 pm

Session 5: Power Components/Subsystems
Session Chair: Herman Chu, Cisco
1 pm – 2:30 pm

Server Power System Trends, Architectures, Technologies, and Issues for Advanced Computing Systems Moving Towards 2010
Joseph (Ted) T. Dibene II, Tomm V. Aldridge, Intel Corporation

The New Hybrid Digital Addressable Lighting Interface Control System
Janusz J. Gondek, Private Institute of Electronic Engineering; Slawomir Kordowiak, Wojciech Mysinski, Cracow University of Technology Institute of Theoretical Electrotechnics and Automatics; Jan Kocol, Technical School of Telecommunication

High Density Computing Rack Solutions to Assure Business Continuity
O. Ray Strickland, Tony Sharp, Sanmina-SCI Corporation

Register On-line

(held in conjunction with the ATW on Thermal Management
October 25-27 - Sheraton Palo Alto)

Housing (Hotel Cut-off is September 24, 2004)
Housing Accommodations must be made directly to:
Sheraton Palo Alto Hotel
625 El Camino Real
Palo Alto, CA 94301
P: 800-874-3516 or 650-328-2800
E: SheratonReservation@pahotel.com
When making reservation, please reference IMAPS
Single/Double: $179
Sheraton Palo Alto Hotel requires a deposit for the first night's room and tax to hold your room. Deposit refunded if reservation is cancelled fourteen (14) days prior to arrival. After which time, deposit is non-refundable.