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Advanced Technology Workshop on
System Level Packaging

Dinah's Garden Hotel
Palo Alto, California - USA
November 10-11, 2011

Extended Early Registration Deadline: October 26, 2011
Hotel Deadline: October 14, 2011

General Chair
Sarosh Patel
Johnstech International
smpatel@Johnstech.com
Tel: 408-733-8731
Technical Co- Chair
Herman Chu
Cisco Systems, Inc.
hchu@cisco.com
Tel: 408-525-1210
Technical Co-Chair
Thomas S. Tarter
Package Science Services LLC
ttarter@pkgscience.com
Tel: 408-969-2388

Organizing Committee:
Dave Copeland, Oracle Corporation
Andy Pfahnl, Devicix, LLC
Jim Knighten, Teradata Corporation

Purchase Workshop CD-Rom

Download "Program" PDF | Speaker Info | Hotel
Co-located with ATW on Thermal Management (Nov 7-9)


As we move to smaller submicron lithography in Silicon and denser packaging the boundaries of the system packaging infrastructure are being constantly challenged. The Advance Technology Workshop on System Packaging is an attempt to bring together leading edge technologies and processes that are currently needed in the System Packaging community to address some challenges associated with higher speed, greater bandwidth, higher system performance efficiency, multidisciplinary trade-offs(e.g. thermal, EMI) and greater densification.

Thurday, November 10th

Registration: 8:00 am - 6:00 pm

Continental Breakfast: 8:00 am - 9:00 am

Opening Remarks: 8:55 am - 9:00 am

Session 1: Optimization of Power Aware Designs
Chair: Andy Pfahnl, Devicix, LLC
9:00 am - 10:30 am

Energy Reduction and Performance Maximization through Improved Cooling 
David Copeland, Oracle 

Thermal Requirements of QSFP modules
Adriana Romero, Electronic Cooling Solutions; Scott Kipp, Brocade 

SFP+ Thermal Enhancements Study
Paul Hattan, Andreas Pfahnl, Devicix, LLC ; Brian Kirk, Zlatan Ljubijankic, Amphenol High Speed Interconnects 

Break: 10:30 am - 11:00 am

Session 2: Electrical Modeling and Simulation of EMC/Signal Integrity/Power Integrity Phenomenon - I
Chair: David Copeland, Oracle
11:00 am - 12:30 pm

Removing Passivity Violations in Via Modeling with Improved Impedance Calculation for an Infinitely Large Parallel-Plane Pair
Dazhao Liu, Yaojiang Zhang, Jun Fan, Missouri University of Science and Technology

Full-Wave EM Simulation of High-Speed IC/Package Designs
Darryl Kostka, Antonio Ciccomancini Scogna, CST of America

Advanced High Density Interconnection PCB For Mobile System Platform Application
Youngdo Kweon, Samsung Electromechanics Co., Ltd.

Lunch: 12:30 pm - 1:30 pm

Session 3:  Electrical Modeling and Simulation of EMC/Signal Integrity/Power Integrity Phenomenon – II
Chair: Thomas S. Tarter, Package Science Services LLC
1:30 pm - 3:00 pm

Analytical Modeling of Coupled TSVs in 3D ICs
A. Ege Engin, Srinidhi Raghavan, San Diego State University

Near Field Coupling of Components and Structures to Ventilation Openings can Reduce Chassis Shielding Effectiveness 
Jeff Evans, Alpesh Bhobe, Cisco Systems, Inc.

LTCC Technology for Wireless System in Package Architecture: Issues & Challenges
Dhirendra Mathur, Govt. Engineering College; S. K. Bhatnagar, CSIR Labs; Vineet Sahula, NIT 

Break: 3:00 pm - 3:30 pm

Session 4:  High Speed Signal Integrity
Chair: Jim Knighten, Teradata Corporation
3:30 pm - 5:00 pm

Crosstalk Re-visited 
Amy J. Chen, Hao Wang, Intel Corporation

ASIC Performance Improvement by Redesigning Its Package
Jianmin Zhang, Jane Lim, Rick Brooks, Loizos Vakanas, Kelvin Qiu, Cisco Systems, Inc.

Design and Optimization Strategies to Mitigate Voltage Noise from Synchronous Buck Converter
Siming Pan, Brice Achkir, Abhilash Rajagopa, Cisco Systems, Inc.

Networking Reception: 5:00 pm - 6:00 pm

Friday, November 11th

Registration: 8:00 am - 1:00 pm

Continental Breakfast: 8:00 am - 9:00 am

Session 5: 3D Vertical Stacked System Packaging
Chair: Herman Chu, Cisco Systems, Inc.
9:00 am - 10:30 am

Design Challenges for 3D Packaging
Thomas S. Tarter, Package Science Services

Alternatives to TSV for chip stacking
Suzette  Pangrle, Vertical Circuits

Silicon Interposers present assembly challenges  
Phil Marcoux, ALLVIA  

Break: 10:30 am - 11:00 am

Session 6: Room Level Design Considerations for IT, Data Center and Service Provider Facilities
Chair: Sarosh Patel, Sarosh Patel Consultancy
11:00 am - 1:00 pm

Design And Management Of Data Center Effectiveness, Risks And Costs
Sherman Ikemoto, Future Facilities 

Achieving Efficiency through Concurrent Design of Hardware and Facility
Veerendra Mulay, Facebook

High-Temperature Computing in Enterprise Environments: Challenges and Opportunities
Niru Kumari, HP Labs

Telco Operators’ Environmental Design Requirements for Network Equipment 
Herman Chu, Cisco Systems, Inc.

Closing Remarks: 1:00 pm

 

 


Speaker Dates/Information:

  • Abstracts due: September 19, 2011
  • Extended Abstracts due: October 11, 2011
  • Powerpoint/Presentation file for CD-Rom due not later than: November 11, 2011
  • Powerpoint/Presentation file used during session: Speaker's responsibility to bring to session on USB and/or CD (recommended to have back-up on personal laptop or email to jmorris@imaps.org prior to event)
  • Technical Presentation Time: 30 minutes (25 to present; 5 for Q&A)

Hotel Information --Hotel Reservation Deadline: October 14, 2011

Dinah’s Garden Hotel
4261 El Camino Real
Palo Alto, CA 94306

Single/Double: $130+ tax per night
Rooms include complimentary wireless internet and parking as well as 15% off meals at Trader Vic's onsite.

Check-in: 3:00pm
Check-out: 12:00pm


Directions/Transportation

From/To San Jose Airport:

The Valley Transportation Authority (VTA) http://www.vta.org/ operates the Airport Flyer, a free shuttle bus http://www.vta.org/schedules/SC_10.html which operates every 15 minutes. The bus stops twice at the airport, once at Terminal A (actually a little bit east of Terminal A, to the right of and across the street from the building with the landing gates and to the left of and on the same side of the street as the building with baggage claim.

The stop for Terminal C is across from the exit from baggage claim, a little bit to the west, left after exiting. Be sure to get on the Westbound bus going to Santa Clara Transit Center, not the Eastbound bus to Metro/Airport Light Rail Station. This is also the same stop as the shuttle buses for Long Term Parking and Rental Cars, so avoid those buses as well. The Westbound bus schedule http://www.vta.org/schedules/SC_10WE_WK.html is also posted on signs at the bus stops.

At the Santa Clara Transit Center, go to the stop for bus number 22 http://www.vta.org/schedules/SC_22.html Westbound to Palo Alto, being sure to avoid riding the 22 Eastbound to Eastridge. The stops for Westbound 22 to Palo Alto and Eastbound 22 to Eastridge are at different locations, so be sure to wait at the correct stop. The bus runs about every 12 minutes http://www.vta.org/schedules/SC_22WE_WK.html and a schedule is also posted at the bus stop. The bus ride costs $1.75 and no change is given, so be sure to have exact fare.

The bus ride takes about 45 minutes. The hotel is located at 4290 El Camino Real, Palo Alto CA 94306, just across the street from Dinah's Court. After stopping at a major bus terminal at El Camino Real and Showers Drive, next to a large shopping center, the bus will pass San Antonio Road, Del Medio Avenue, Cesano Court (there will be a bus stop at Cesano Court), Monroe Drive and Dinah's Court. The nearest bus stop is just after Dinah's Court, pull the cord to inform the driver that you wish to stop after passing the Cesano Court bus stop. Between San Antonio Road and Dinah's Court the bus will pass the San Antonio Inn, Holiday Inn Express, Country Inn Motel, Motel 6 and Oak Motel on the right before the bus stop at Dinah's Garden Hotel. The Crowne Plaza Cabana is directly across the street from Dinah's.

From/To San Francisco Airport:

The San Francisco subway system, Bay Area Rapid Transit (BART) http://bart.gov/ has a station in the International Terminal. The trip from the airport to Millbrae station takes 11 minutes and costs $1.50.

From the airport, take the train four minutes to the first stop, San Bruno. At San Bruno, change to the train across the platform for Millbrae. There is only a four minute wait. From San Bruno to Millbrae requires five minutes. Trains operate every 15 minutes most of the day, detailed schedules are found at http://bart.gov/schedules/index.aspx

From Millbrae, the next ride is on Caltrain http://caltrain.org/ to Palo Alto, which takes 30 or 32 minutes mid-day (longer on evenings and weekends) and costs $4.00. Be sure to ride the Southbound train toward San Jose and not the Northbound train toward San Francisco. Tickets must be purchased before boarding the train. Schedules are found at http://caltrain.org/timetable.html

From Palo Alto Transit Center, go to the stop for bus number 22 http://www.vta.org/schedules/SC_22.html Eastbound to Eastridge. The bus runs about every 12 minutes http://www.vta.org/schedules/SC_22EA_WK.html and costs $1.75. No change is given, so be sure to have exact fare. The bus ride takes about 16 minutes. The bus will pass Page Mill Road, Super 8 Motel, Creekside Inn and Townhouse Inn on the right, then cross Arastradero Road, then pass America's Best Value Inn and Days Inn. The Crowne Plaza Cabana will be on the right with a bus stop in front. Please pull the cord to inform the driver that you wish to stop shortly after passing the bus stop near Arastradero Road.

 




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