Advanced
Technology Workshop on
System Level Packaging
Dinah's Garden Hotel
Palo Alto, California - USA
November 10-11, 2011
General
Chair
Sarosh Patel
Johnstech International
smpatel@Johnstech.com
Tel: 408-733-8731
|
Technical Co-
Chair
Herman Chu
Cisco Systems, Inc.
hchu@cisco.com
Tel: 408-525-1210
|
Technical Co-Chair
Thomas S. Tarter
Package Science Services LLC
ttarter@pkgscience.com
Tel: 408-969-2388
|
Organizing Committee:
Dave Copeland, Oracle Corporation
Andy Pfahnl, Devicix, LLC
Jim Knighten, Teradata Corporation
|
Purchase Workshop CD-Rom
Co-located with ATW on Thermal Management (Nov 7-9)
As we move to smaller submicron lithography in Silicon and denser packaging the boundaries of the system packaging infrastructure are being constantly challenged. The Advance Technology Workshop on System Packaging is an attempt to bring together leading edge technologies and processes that are currently needed in the System Packaging community to address some challenges associated with higher speed, greater bandwidth, higher system performance efficiency, multidisciplinary trade-offs(e.g. thermal, EMI) and greater densification.
Thurday, November 10th
Registration: 8:00 am - 6:00 pm
Continental Breakfast: 8:00 am - 9:00 am
Opening Remarks: 8:55 am - 9:00 am
Session 1: Optimization of Power Aware Designs
Chair: Andy Pfahnl, Devicix, LLC
9:00 am - 10:30 am
Energy Reduction and Performance Maximization through Improved Cooling
David Copeland, Oracle
Thermal Requirements of QSFP modules
Adriana Romero, Electronic Cooling Solutions; Scott Kipp, Brocade
SFP+ Thermal Enhancements Study
Paul Hattan, Andreas Pfahnl, Devicix, LLC ; Brian Kirk, Zlatan Ljubijankic, Amphenol High Speed Interconnects
Break: 10:30 am - 11:00 am
Session 2: Electrical Modeling and Simulation of EMC/Signal Integrity/Power Integrity Phenomenon - I
Chair: David Copeland, Oracle
11:00 am - 12:30 pm
Removing Passivity Violations in Via Modeling with Improved Impedance Calculation for an Infinitely Large Parallel-Plane Pair
Dazhao Liu, Yaojiang Zhang, Jun Fan, Missouri University of Science and Technology
Full-Wave EM Simulation of High-Speed IC/Package Designs
Darryl Kostka, Antonio Ciccomancini Scogna, CST of America
Advanced High Density Interconnection PCB For Mobile System Platform Application
Youngdo Kweon, Samsung Electromechanics Co., Ltd.
Lunch: 12:30 pm - 1:30 pm
Session 3: Electrical Modeling and Simulation of EMC/Signal Integrity/Power Integrity Phenomenon – II
Chair: Thomas S. Tarter, Package Science Services LLC
1:30 pm - 3:00 pm
Analytical Modeling of Coupled TSVs in 3D ICs
A. Ege Engin, Srinidhi Raghavan, San Diego State University
Near Field Coupling of Components and Structures to Ventilation Openings can Reduce Chassis Shielding Effectiveness
Jeff Evans, Alpesh Bhobe, Cisco Systems, Inc.
LTCC Technology for Wireless System in Package Architecture: Issues & Challenges
Dhirendra Mathur, Govt. Engineering College; S. K. Bhatnagar, CSIR Labs; Vineet Sahula, NIT
Break: 3:00 pm - 3:30 pm
Session 4: High Speed Signal Integrity
Chair: Jim Knighten, Teradata Corporation
3:30 pm - 5:00 pm
Crosstalk Re-visited
Amy J. Chen, Hao Wang, Intel Corporation
ASIC Performance Improvement by Redesigning Its Package
Jianmin Zhang, Jane Lim, Rick Brooks, Loizos Vakanas, Kelvin Qiu, Cisco Systems, Inc.
Design and Optimization Strategies to Mitigate Voltage Noise from Synchronous Buck Converter
Siming Pan, Brice Achkir, Abhilash Rajagopa, Cisco Systems, Inc.
Networking Reception: 5:00 pm - 6:00 pm
Friday, November 11th
Registration: 8:00 am - 1:00 pm
Continental Breakfast: 8:00 am - 9:00 am
Session 5: 3D Vertical Stacked System Packaging
Chair: Herman Chu, Cisco Systems, Inc.
9:00 am - 10:30 am
Design Challenges for 3D Packaging
Thomas S. Tarter, Package Science Services
Alternatives to TSV for chip stacking
Suzette Pangrle, Vertical Circuits
Silicon Interposers present assembly challenges
Phil Marcoux, ALLVIA
Break: 10:30 am - 11:00 am
Session 6: Room Level Design Considerations for IT, Data Center and Service Provider Facilities
Chair: Sarosh Patel, Sarosh Patel Consultancy
11:00 am - 1:00 pm
Design And Management Of Data Center Effectiveness, Risks And Costs
Sherman Ikemoto, Future Facilities
Achieving Efficiency through Concurrent Design of Hardware and Facility
Veerendra Mulay, Facebook
High-Temperature Computing in Enterprise Environments: Challenges and Opportunities
Niru Kumari, HP Labs
Telco Operators’ Environmental Design Requirements for Network Equipment
Herman Chu, Cisco Systems, Inc.
Closing Remarks: 1:00 pm
