IMAPS PDC Webinar Series on
Wire Bonding

This two-session on-line Professional Development Course (PDC) webinar was held:
Thursday, January 29 and Thursday, February 5, 2009
All webinars were held 12:00 noon - 1:00 pm EST

Registration:
IMAPS Members: $125 per webinar; 2-course series $200
Non-members: $200 per webinar; 2-course series $375

Click on the linked Webinar Titles below to purchase/download

Key Words

Wire bond, intermetallic, ultrasonic welding, semiconductor packaging, BGA. 3D packaging, SOP

Program Description

Wire bonding remains the dominant chip interconnect method, with more than 90% of the chip interconnect market place. The ultrasonic weld produced by wire bonding has proven to be a highly reliable and versatile form of interconnection, and the process has continuously evolved to meet the demands of increasingly complex devices.

These 2 one-hour PDC lectures that can be taken in total or separately depending on the experience level of the student and topics of interest.  Below is a course outline for each session.  Each session is scheduled for 50 minutes of lecture followed by 10 minutes of Q&A.

Session 1 of 2: Thursday, January 29 -- 12:00-1:00 PM EST

In Session 1 we will focus on the wire bonding process and variations.

• Background
• The ball bonding process: Step by Step Wire Bonding
• Welding
• The effect of ultrasonics on weld formation and materials properties
• Diffusion
• Metallurgy and Intermetallics
• A comparison of the welds associated with Au-Al and Cu-Al bonding
• Au-Al failure mechanisms in ultra-fine pitch bonding
• The effect of wire alloying on the reliability of Au-Al ball bonds

Session 2 of 2: Thursday, February 5 -- 12:00-1:00 PM EST

In Session 2 we will focus on the process variables and the use of Designed Experiments to understand the process.

• Wire bonding process variables
• Testing wire bonds and response variables
• The use of Designed Experiments to understand a complex process
• Experiments for high yield processes
• Analysis methods
  • DOE Analysis
  • Pareto diagrams
  • Control charts for high yield processes

Presenter Lee is an internationally recognized semiconductor assembly process expert with over 25 years of targeted experience in technical process development and optimization. He is known for keen analytical and troubleshooting skills in the creative and effective resolution of problems in production processes. He consistently produces business results that create enhanced revenue opportunities, higher yields and trouble free operations. Previous experience includes 20 years as Principal and Staff Metallurgical Process Engineer at Kulicke & Soffa and Distinguished Member of the Technical Staff at Agere Systems. He was awarded 4 patents, published more than 50 technical papers, and won the 1999 John A. Wagnon Technical Achievement award from the International Microelectronics and Packaging Society, IMAPS. Major innovations include copper ball bonding, loop shapes for thin, small outline packages (TSOP and TSSOP, and CSPs) and introduction of DOE and statistical techniques for understanding assembly processes. He is a Fellow, V.P of the Keystone Chapter, and V.P Technology for IMAPS. Lee is a graduate of Lehigh University, Bethlehem, Pa where he earned a degree in Metallurgy and Materials Engineering.