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IMAPS PDC Webinar Series on
Signal Integrity and Precision Design in Digital Systems

This three-session on-line Professional Development Course (PDC) webinar was held:
Wednesdays, May 6, 13, and 20, 2009

All webinars were held 12:00 noon - 1:00 pm EST

Registration:
IMAPS Members: $125 per webinar; 3-course series $250
Non-members: $200 per webinar; 3-course series $500

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Key Words

Signal integrity, precision design, digital system, interconnect, electrical performance, bandwidth, modeling, simulation, measurement, characterization, verification, loss, reflection, crosstalk, eye-diagram, S-parameter, skew, jitter

Program Description

Signal integrity margin keeps shrinking as electrical interconnect bandwidth increases. Accurate modeling and design trade-offs are required to achieve product electrical specifications and maintain system cost-effectiveness.

This professional development course provides the knowledge and skills required for the precision design of electrical interconnections. The course starts with a review of fundamental concepts of signal integrity in digital systems, followed by signal propagation along transmission lines and various discontinuities. Packaging structures which degrade signal integrity will be discussed, including their contribution to insertion loss, reflective ringing, and crosstalk.

Signal integrity analysis techniques will also be covered. With some example cases, the definition and interpretation of frequency domain S-parameters are introduced then correlated to time-domain eye-diagrams and impulse responses for “eye” quality, skew and jitter analysis. The power spectral density of signals as a function of data-rate, pattern, and waveform shape will also be discussed.

Modeling strategies designed to analyze signal integrity of system-level links will be presented with examples employing commercial modeling software. The criteria of model segmentation and setup are described as well as the importance of verifying models by correlating them with measurements. Both frequency-domain and time-domain link-level simulations will be demonstrated, followed by comparisons of different signaling schemes (S.E. vs. Differential) and effects of various equalization choices.

Hardware characterization is often a difficult task at high frequencies due to the parasitics of accessing the device under test (through vias or connectors not part of the desired structure). Measurements, calibration and structural de-embedding will be discussed for commonly used equipment such as vector network analyzers, time-domain reflectometers, and oscilloscopes.  

Finally, the effects of design and manufacturing tolerance will be discussed, including perforations on reference planes, high-density buses, power/ground mixed-referencing, layer misalignment, and material/geometry variations.

These 3 one-hour PDC lectures can be taken in total or separately depending on the experience level of the student and topics of interest.  Below is a course outline for each session.  Each session is scheduled for 50 minutes of lecture followed by 10 minutes of Q&A.

Session 1 of 3: Wednesday, May 6 -- 12:00-1:00 PM EST

  • Introduction of signal integrity in digital systems
  • Signal propagation along transmission lines and various discontinuities
  • Packaging structures and their electrical characteristics
  • Electrical analysis: frequency domain
    • S-parameters
    • Insertion loss, reflection, crosstalk

Session 2 of 3: Wednesday, May 13 -- 12:00-1:00 PM EST

  • Electrical analysis: time domain
    • Impulse response, delay
    • Eye-diagram, skew, jitter
  • Power spectral density of digital signal
    • Data-rate, rise/fall time, pattern
    • Correlations: frequency-domain vs. time-domain
  • Mixed-referencing and system-level modeling strategies
    • Approaching to system-level designs
    • Effects of non-ideal return paths and power noise
  • Criteria of model segmentation and setup
    • 2D vs. 3D
    • Model dimensions
    • Ports and boundary condition

Session 3 of 3: Wednesday, May 20 -- 12:00-1:00 PM EST

  • Signaling scheme and equalization choices
    • Single Ended vs. Differential
    • Equalization choices
  • Measurement and calibration techniques
    • Calibration, de-embedding
    • VNA, TDR/TDT, BERT
  • Design and manufacturing tolerance
    • Design trade-offs
    • Manufacturing tolerance and the effects

Who Should Attend?

The course covers both fundamental knowledge and advanced analysis/characterization skills. Therefore, it is not only suitable for electrical engineers/managers, but also system designers who need to balance chip/packaging or electrical/mechanical trade-offs. Newcomers may also take it to jump start their careers.

Thomas Green

Presenter

Lei Shan received his MS in Electrical Engineering and Ph.D. in Mechanical Engineering from Georgia Institute of Technology in 2000. In 2001, he joined IBM T.J. Watson Research Center, Yorktown Heights, NY, as a Research Staff Member, where he works on high speed electronics/optoelectronics packaging designs and multi-physics modeling/simulations. He designed and demonstrated high speed packages on both connectorized format and BGA joints for 50Gbps multiplexer and demultiplexer based on IBM SiGe BiCMOS technology. He led the packaging development for 10G Ethernet and Terabus optical links on printed circuit board. His recent research interest is on precision designs and signal/power integrity in high-performance computing systems and the fundamental electrical limits. Shan has authored over 40 publications with three Best Paper Awards and owns over 20 US patents.


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