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IMAPS PDC Webinar Series on
Introduction to Microelectronics Packaging Technology

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This three-session on-line Professional Development Course (PDC) webinar were held:
Wednesdays, February 3, 10, and 17, 2010

All webinars were held 12:00 noon - 1:00 pm EST

IMAPS Members: $125 per webinar; 3-course series $250
Non-members: $200 per webinar; 3-course series $500

Key Words

Introduction microelectronics packaging technology, BEOL, photolithography, MEMS, RFID, backgrinding, wafer sawing, die attach, wire bond, hermetic sealing, solder wave packages, BGA, flip chip, 3D packaging, 3D-IC TSV, SoC, SiP, SOP, SMT, green microelectronics

Program Description

This updated on-line PDC provides an introduction to microelectronics packaging technology to entry-level engineers and technicians involved in manufacturing, processing, R&D, quality, sales and marketing. No prior knowledge of microelectronics is required. Emphasis will be on a variety of photos and figures to provide the student with not only a solid base in how various microcircuits are made by many materials, processes and equipment, but also what they physically look like. Students will learn basic microelectronic packaging definitions as well as current state of the art terminology of materials, processes and equipment, including various relevant technologies in microelectronics and semiconductor processing.

New developments will be discussed as applied to MEMS, SiP, RFID, Thin Chips/3D/WLP, Thru-Silicon Vias, and Green Technology. An overview of major industry leaders and their new technologies will include Intel's 32nm process, IBM's C4NP, Freescale's RCP, Samsung's TSV, Amkor's SiP & SoP, and others.

This on-line PDC is a series of 3 one-hour lectures that can be taken in total or separately depending on the experience level of the student and topics of interest.  Below is a course outline for each session.  Each session is scheduled for 50 minutes of lecture followed by 10 minutes of Q&A.

Session 1 of 3: Wednesday, February 3 -- 12:00-1:00 PM EST

The multi-billion dollar microelectronics global market reflects the most dynamic and rapidly growing industry in the world and is faced with constantly changing technology and challenges every year.

This lead-off session provides an overview of the top companies and application areas along with different perspectives of the microelectronics process, setting our background for reviewing the often-referenced Moore's Law, the classic microelectronics package, the relationship with Nanotechnology and the first part of the packaging process:

  • Design
  • Basic Front End of Line Processes
  • Basic Wafer Processing (masks, photolithography, deposition, etching, doping)
  • Basic Back End of Line Processes (BEOL – dielectric, metallization, wafer probing, backgrinding/thinning, packaging)
  • Micro-Electro-Mechanical Systems (MEMS)
  • Wafer Level Packaging (WLP)
  • Flip Chip Wafer Bumping  

In the second part of this session we’ll examine 1st Level Technologies and Related Packages (Single and Multi-Chip) which include topics on:

  • Active and Passive Devices
  • Popularity of Package Types
  • Hierarchy of Packaging
  • Basic Leaded Solder Wave Packages (SIP, DIP, PGA, DFP, QFP)
  • Basic Leaded and Leadless Surface Mount Technology (SMT) Types (SO, SOIC, DFP, QFP, QFN)
  • Ball Grid Arrays (BGA) and Plastic Over Molded Lead Frames
  • Advanced Packaging (Chip Scale Packaging [CSP], Flip Chip [FC], 3D Packaging, Multi-Chip Substrates and Modules)
  • Overview of Assembly Process

Session 2 of 3: Wednesday, February 10 -- 12:00-1:00 PM EST

This second session in the series will include a more detailed and specific discussion on Assembly Processing and Packaging:

  • Wafer Sawing
  • Die Attach (epoxy, eutectic, silver glass, equipment, epoxy vs. eutectic, epoxy bleed)
  • Wire Bonding (bond types, bond formation, successful bonding, Tape Automated Bonding [TAB], flip chip)
  • Package Sealing (hermeticity, near hermeticity, Chip On Board [COB], glob top, dam and fill)
  • Flip Chip (solder, polymer, stud bump, underfill, equipment)
  • Mid/Low End Packaging
  • High End Packaging
  • 3D Package on Package (PoP)
  • 3D Stacked Die (wire bond)
  • 3D Microsystems (System on Chip [SoC], System in Package [SiP], System On Package [SOP])
  • 3D IC (Thru-Silicon Vias [TSV], why it's popular, basic structure, process, 3D-IC TSV)
  • Packaging Nomenclature Fundamentals
  • Clean Rooms

Session 3 of 3: Wednesday, February 17 -- 12:00-1:00 PM EST

The final session will progress to the 2nd Level and System Level of Packaging which include board assembly and other important system considerations:

  • Surface Mount Technology (SMT) Assembly Line
  • Lead Free Solder Recommendations
  • Tin Whisker Mitigation
  • Rework and Repair
  • Final Assembly, Test and Failure Analysis
  • Quality and Reliability
  • Electro-Static Discharge
  • Safety
  • Green Technology (RoHS, WEEE, REACH)

The second part of this session will provide a review of state of the art innovations of packaging industry leaders:

  • Intel (65 nm processor, Hi-K/Metal Gates, 45 nm processor, Top Suppliers)
  • IBM (Hi-K/Metal Gates, Lo-K dielectric, TSV, Power 65nm processor, ASICs, C4NP)
  • Freescale (Redistributed Chip Package, Package on Package)
  • Samsung (EMC-3D, WSP and TSV)
  • Amkor (Process Steps, Turnkey, Flip Chip, WLP, 3D, MLF, SiP)
  • STATSChipPAC (Turnkey, TSV, PoP)

Students will have access to all the course slides and in addition will receive a complete set of references/web links providing not only the source material but links to additional detailed information on all main topics covered.

Also included is a complimentary copy of a detailed Glossary of Microelectronic Packaging Terms.

Who Should Attend?

No prior knowledge of microelectronics is required since this course is designed for the student who has little initial familiarity with Microelectronics Packaging engineering but would like to relate it to real life, everyday applications. The course uses simple terms for ease of understanding yet includes aspects of advanced packaging for senior engineers new to the field and needing a running start in packaging technology. Ideal for entry level technicians and engineers and also for people in quality assurance, sales, marketing, purchasing, safety, administration and program management.

Thomas Green


Phillip Creter has over 30 years of microelectronics packaging experience and is a Life member of IMAPS. He was elected a Fellow of the Society, National Treasurer and President of the New England Chapter (twice). He received a BS in Chemistry with honors from Suffolk University and has published numerous papers, holds a U.S. patent, has made many technical presentations (received Best Paper of Session award IMAPS) and chaired numerous technical sessions for symposia. He is currently a consultant (Creter & Associates) gaining his microelectronics packaging experience at Polymer Flip Chip Corporation, Mini-Systems, GTE and Itek Corporation. His past positions include GTE Microelectronics Center Manager (receiving coveted corporate Lesley Warner Technical Achievement Award), Process Engineering Manager, Process Development Manager, Materials Engineering Manager and Manufacturing Engineer. Phil currently teaches professional development courses at microelectronics events and is an active certified instructor for the Department of Homeland Security.

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