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IMAPS PDC Webinar Series on
Package on Package (PoP) Applications,
Requirements, Infrastructure and Technologies

This three-session on-line Professional Development Course (PDC) webinar was held:
Thursdays March 18, 25 and April 1

All webinars were held 12:00 noon - 1:00 pm EST

IMAPS Members: $125 per webinar; 3-course series $250
Non-members: $200 per webinar; 3-course series $500

Registration Deadline: March 17, 2010

Key Words

Package on Package, PoP, 3D Packaging, Stacked Packaging, Packaging for hand held devices (meaning cellphones, cameras, USB devices, etc)

Program Description

Course Scope:
This course will take an in depth view of the applications, market requirements, supply chain infrastructure and technologies associated with the BGA package stacking platform commonly referred to as package on package (PoP).

What you will learn:
This course will help you decide when and how, PoP technology can provide system level semiconductor integration benefits. How you can evaluate and select the optimum PoP technology for you applications by understanding the complex mix of cost, performance and business / logistic benefits PoP provides. Where industry standards, device floor-planning and supply chain infrastructures can reduce the total cost or time to market when implementing a PoP solution. How the PoP platform aligns with industry roadmaps to meet the higher density challenges associated with next generation device integration and system design requirements. What the key PoP design related parameters are and how they relate to package sizing and selection.

PoP Technologies and Infrastructure covered will include:
The top PoP which is typically a memory component using stacked die multi-chip package technology to integrates a combination of memory devices. The associated JEDEC memory interface standards will be highlighted.

The bottom PoP which is typically a logic component using advanced high density thin core substrate technology with special design and material properties to enable integration of a high density mobile processor device and support stacking of combination memory top package. Enabling technologies, and JEDEC mechanical design guidelines will be summarized.

The PoP infrastructure - including SMT stacking, pre-stacking and joint industry studies for stacking and board level reliability testing will be presented.

A section of the course will review real world high volume PoP applications used in multimedia mobile handsets based on industry teardown reports. Quantify the technical and business / logistic factors that make up the total cost of ownership benefits which has been major driver of broad industry adoption of the PoP technology. The course will explore the critical role industry infrastructure development and JEDEC standards have played in the high rates of PoP adoption in mobile multimedia applications.

This on-line PDC is a series of 3 one-hour lectures that can be taken in total or separately depending on the experience level of the student and topics of interest.  Below is a course outline for each session.  Each session is scheduled for 50 minutes of lecture followed by 10 minutes of Q&A.

Session 1 of 3: Thursday, March 18 -- 12:00-1:00 PM EST

  • An introduction to Package on Package (PoP) terminology
  • Progression of packaging from 1D to 3D
  • Comparison of Stacked die to Stacked Package (PoP) to Package-in-Package (PiP)
  • Discussion of PoP Design Considerations
  • Discussion of PoP JEDEC standardization

Session 2 of 3: Thursday, March 25 -- 12:00-1:00 PM EST

  • PoP net hierarchy and functional test considerations for design
  • Discussion of warpage and how it affect PoP
  • Review of the various PoP surface mount stacking methods

Session 3 of 3: Thursday, April 1 -- 12:00-1:00 PM EST

  • Industry generated PoP board level reliability data
  • Future developments in PoP including TMV (Thru Mold Via) and SOP (Solder on Pad)
Thomas Green


Moody Dreiza’s current responsibilities are in the field of product management associated with Amkor Technology’s stacked package (PoP) product line.

Moody’s previous experience includes four years in Amkor’s design center supporting CSP and PBGA design and design tool automation.

Moody has earned a Bachelor’s degree in Mechanical Engineering from the University of Manchester Institute of Science and Technology (UMIST) in Manchester, England.

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Phone: 202-548-4001