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IMAPS PDC Webinar Series on
Introduction to Microelectronics Packaging Including Industry Updates and Trends

This three-session on-line Professional Development Course (PDC) webinar will be held:
NEW DATES: Mondays, April 4, 11, and 18, 2011

All webinars will be held 12:00 noon - 1:00 pm EDT

Registration:
IMAPS Members: $125 per webinar; 3-course series $250
Non-members: $200 per webinar; 3-course series $500

Registration Deadline: April 3, 2011

Register On-Line


Key Words

Introduction microelectronics packaging, microelectronics industry update and trends, BEOL, MEMS, RFID, backgrinding, wafer sawing, die attach, wire bond, hermetic sealing, solder wave packages, BGA, flip chip, 3D packaging, 3D-IC TSV, interposers, SoC, SiP, SOP, SMT, eWLB, RCP, IMAPS, ITRS, C4NP/IMS, green microelectronics, Intel, IBM, Freescale, Samsung, Amkor, STATSChipPAC

Program Description

This on-line PDC provides an introduction to microelectronics packaging technology with related updates in industry trends for entry-level engineers and technicians involved in manufacturing, processing, R&D, quality, sales and marketing. No prior knowledge of microelectronics is required. Emphasis will be on a variety of photos and figures to provide the student with not only a solid base in how various microcircuits are made by many materials, processes and equipment, but also what they physically look like. Students will learn basic microelectronic packaging definitions as well as current state of the art terminology of materials, processes and equipment, including various relevant technologies in microelectronics and semiconductor processing.

New developments will be discussed as applied to MEMS, SiP, RFID, Thin Chips, 2D/2.5D/3D/WLP, Thru-Silicon Vias, interposers and Green Technology. An overview of major industry leaders and their new technologies will include Intel's 32nm process and Sandy Bridge, IBM's C4NP/IMS, Freescale's RCP update, Samsung's packaging capability, Amkor's Fine Pitch Copper Pillar Bumps, STATSChipPAC’s Fan-In/Fan-Out eWLB Packaging and Chip Embedding.

This on-line PDC is a series of 3 lectures that can be taken in total or separately depending on the experience level of the student and topics of interest. Below is a course outline for each session. Each session is scheduled for 50 minutes of lecture followed by 10 minutes of Q&A.

Session 1 of 3: Monday, April 4 -- 12:00-1:00 PM EDT

The multi-billion dollar microelectronics global market reflects the most dynamic and rapidly growing industry in the world and is faced with constantly changing technology and challenges.

This lead-off session provides an overview of the top companies and application areas along with different perspectives of the microelectronics process, setting our background for reviewing the often-referenced Moore's Law, the classic microelectronics package, the relationship with Nanotechnology and the initial part of the packaging process:

  • Design
  • Basic Front End of Line Processes
  • Basic Wafer Processing (masks, photolithography, deposition, etching, doping)
  • Basic Back End of Line Processes (BEOL – dielectric, metallization, wafer probing, backgrinding/thinning, packaging)
  • Micro-Electro-Mechanical Systems (MEMS)
  • Wafer Level Packaging (WLP)
  • Flip Chip Wafer Bumping  

In the second part of this session we’ll examine 1st Level Technologies and Related Packages (Single and Multi-Chip) which include topics on:

  • Active and Passive Devices
  • Popularity of Package Types
  • Hierarchy of Packaging
  • Basic Leaded Solder Wave Packages (SIP, DIP, PGA, DFP, QFP)
  • Basic Leaded and Leadless Surface Mount Technology (SMT) Types (SO, SOIC, DFP, QFP, QFN)
  • Ball Grid Arrays (BGA) and Plastic Over Molded Lead Frames
  • Advanced Packaging (Chip Scale Packaging [CSP], Flip Chip [FC], 3D Packaging, Multi-Chip Substrates and Modules)
  • Overview of Assembly Process

Session 2 of 3: Monday, April 11 -- 12:00-1:00 PM EDT

This second session in the series will include a more detailed and specific discussion on Assembly Processing and Packaging:

  • Wafer Sawing
  • Die Attach (polymer, silver glass frit, eutectic, SMT process with solder and polymer, sintered nanosilver, flip chip, equipment, epoxy vs. eutectic, epoxy bleed)
  • Wire Bonding (bond types, bond formation, successful bonding, Tape Automated Bonding [TAB], flip chip)
  • Package Sealing (hermeticity, near hermeticity, Chip On Board [COB], glob top, dam and fill)
  • Flip Chip Details (UBM, solder and polymer bumps, stud bump, underfill, equipment)
  • Mid/Low End Packaging
  • High End Packaging
  • 3D Package Evolution (3D Definitions, Current Levels of Packaging)
  • 3D Levels of Complexity
  • 3D Microsystems (System on Chip [SoC], System in Package [SiP], System On Package [SOP])
  • 3D IC (Current Market, Not Ready for Prime Time)
  • 2.5D/3D Silicon TSV, Interposers
  • Wafer-Scale Level Processing (Fan-In/Fan-Out, eWLB)
  • Packaging Nomenclature Fundamentals
  • Clean Rooms

Session 3 of 3: Monday, April 18 -- 12:00-1:00 PM EDT

The final session will progress to the 2nd Level and System Level of Packaging which include board assembly and other important system considerations:

  • Surface Mount Technology (SMT) Assembly Line
  • Lead Free Solder Recommendations
  • Tin Whisker Mitigation
  • Rework and Repair
  • Final Assembly, Test and Failure Analysis
  • Reliability
  • Electro-Static Discharge
  • Safety
  • Green Technology (RoHS, WEEE, REACH)

The second part of this session will provide a review of state of the art innovations of packaging industry leaders:

  • Intel (45 nm processor, Hi-K/Metal Gates, 32 nm processor, Sandy Bridge, Top Suppliers)
  • IBM (Chip Connection Controlled Collapse New Process, Mask and Mask-less Injection Molded Solder [IMS] technology)
  • Freescale (Redistributed Chip Package [RCP] Update)
  • Samsung (32nm Hi-K qualification, packaging capability)
  • Amkor (Process Steps, Turnkey, Flip Chip Fine Pitch Copper Pillar Bumps)
  • STATSChipPAC (Fan-In/Fan-Out, eWLB, Chip Embedding)

Students will have access to all the course slides and in addition will receive a complete set of over 200 references/web links providing not only the source material but links to additional detailed information on all main topics covered.

Also included is a complimentary copy of a detailed Glossary of Microelectronic Packaging Terms.

Who Should Attend?

No prior knowledge of microelectronics is required since this course is designed for the student who has little initial familiarity with Microelectronics Packaging engineering but would like to relate it to real life, everyday applications. The course uses simple terms for ease of understanding yet includes aspects of advanced packaging and industry updates and trends for senior engineers new to the field and needing a running start in packaging technology. Ideal for entry level technicians and engineers and also for people in quality assurance, sales, marketing, purchasing, safety, administration and program management.

Thomas Green

Presenter

Phillip Creter has over 30 years of microelectronics packaging experience. He is currently a consultant (Creter & Associates) gaining his microelectronics packaging experience at Polymer Flip Chip Corporation, Mini-Systems, GTE and Itek Corporation. His past positions include GTE Microelectronics Center Manager (received GTE Corporate Lesley Warner Technical Achievement Award), Process Engineering Manager, Process Development Manager, Materials Engineering Manager, and Manufacturing Engineer. He has published more than a dozen technical papers, holds a U.S. patent, has given over twenty technical presentations, and has chaired numerous technical sessions for symposia. He has been teaching microelectronics courses at the college level since 1997 and since 2004, has continuously taught professional development courses at various symposia and workshops, recently adding online microelectronics webinars. He is an active certified instructor for the Department of Homeland Security currently teaching courses locally. He is a Life member of IMAPS. He was elected Fellow of the Society, National Treasurer and President of the New England Chapter (twice).

Register On-Line


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