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IMAPS PDC Webinar Series on
Microelectronics Packaging Industry Updates and Trends

This two-session on-line Professional Development Course (PDC) webinar will be held:
Wednesdays, April 18, and 25, 2012

All webinars will be held 12:00 noon - 1:00 pm EASTERN

IMAPS Members: $125 per webinar; 2-course series $200
Non-members: $200 per webinar; 2-course series $375


Key Words

3DIC, AC2W, back end wafer processing, C4NP, carrier wafer, copper pillar, copper wire, embedded chip, eutectic, eWLB, flip chip, future packaging trends, interconnect gap, interposer, iPhone, ITRS, iUHD, LED, MEMS, nanosilver, PoP, QFN, SiP, SoC, Taiko wafer, wafer level packaging, wafer level underfill

Program Description

This NEW webinar (including leading edge technical developments through early 2012) features the latest in microelectronics updates and trends for all levels of technical experience.

The course concept is to provide technologists, who have limited available time, the ability to review new microelectronics packaging developments in a compact package. The instructor is a semi-retired technologist who has the luxury of time to review technical papers and daily news accounts and concentrate the data in an organized structure that is backed up by the specific reference. If a discussed topic is of further interest, the format allows easy access to more detail via the internet.

This course provides an update in technology trends based mostly on selected highlights of recent leading edge packaging papers presented at major symposia. Over 450 papers and 100 news items were reviewed for relevant inclusion in the following subject areas:

Backend Wafer Processing (Copper Pillar, Wafer Level Flip Chip Underfill, MEMS) Handling Thin Wafers (Taiko Carrier-less, 150 Micron Modified Taiko, 50 Micron Carrier) Chip Attach (Eutectic, Nanosilver) Interconnect (Copper Wire Bonding) Packaging (QFNs, Flip Chip, LEDs, Embedded Chips, 2.5D/3D Interposers, 3D Pop and 3D-IC, SiP and SoC)

A short review of the basic packaging steps precedes the review of timely topics in order to allow easy understanding by an attendee with no prior knowledge of microelectronics packaging.

Industry sources of technical innovations used in this review are from A*Star, Amkor, Asymtek, Chip Scale Review, Chip Works, Cisco, Digitimes, Disco, Draper Laboratory, ECTC, EE Times, EERE, ElectroIQ, Electronic Trend Publications, Failure-Free Integrated Circuit Packages, Freescale, Georgia Institute of Technology, Hong Kong University, Huazhong University, IBM, IC Insights, IFTLE, IMAPS, IMEC, INEMI, IPC, Infineon, Intel, iSuppli, ITRI, ITRS, JEDEC, K&S Industries, Luminous Devices, MacDermid Electronic Solutions, Micronews, MIT, NBE Tech, Newport Industry, Palomar Technologies, RJR Polymers, Samsung, Sandia National Labs, Schweizer Electronic AG, Scribd, Sematech, Semiconductor International, Semiconductor Packaging News, Semiconwest, SiliconFarEast, Solid State Technology, STATSChipPAC, TechSearch, TSMC and Yole Developpement.

Below is a course outline for each session. Each session is scheduled for 50 minutes of lecture followed by 10 minutes of Q&A.

Session 1 of 2: Wednesday, April 18 -- 12:00-1:00 PM EASTERN

  • Basic Review
    • Market/Industry Ranking/Market Drivers
    • Apple iPhone 4S Example
    • Interconnect Gap/Packaging Overview/Evolution/Types/Ultimate Package Definition
    • Mainstream of Package Types
    • Future Trends for Wafer Level Packaging
    • Levels of Packaging Process
    • Back End of Line Packaging Applications/Single Chip Packaging/Assembly Process
  • Updates & Trends
    • Backend Wafer Processing
      • Copper Pillar (ST Microelectronics, Amkor)
      • Wafer Level Flip Chip Underfill (IBM OBAR, Sumitomo No Flow)
      • MEMS (Sandia Wafer Level Capping)
    • Handling Thin Wafers
      • Taiko Carrier-Less (Disco)
      • 150 micron Modified Taiko (Doublecheck Semiconductors)
      • 50 micron Carrier (A*Star)
    • Chip Attach
      • Eutectic (Palomar, Newport)
      • Nanosilver (NBE Tech)
    • Interconnect
      • Copper Wire (K&S, Freescale, Cisco, Sumitomo, ASE)

Session 2 of 2: Wednesday, April 25 -- 12:00-1:00 PM EASTERN

  • Packaging
    • QFNs (Amkor, RJR Polymers, MacDermid Electronic Solutions)
    • Flip Chip (Qualcomm, IBM)
    • LEDs (EERE, Yole, Huazhong University of Science &Technology, Hong Kong University of Science and Technology)
    • Embedded Chip/Wafer (ITRS, Schweizer Electronic AG, Infineon)
    • 2.5D/3D Interposers (Georgia Institute of Technology, Taiwan Semiconductor Manufacturing Company)
    • 3D PoP (Amkor)
    • 3DIC (Imec, Samsung)
  • Industry Leaders
    • Intel (Sandy Bridge, Ivy Bridge)
    • IBM (C4NP, Advanced Chip to Wafer Process—AC2W)
    • Draper Labs (Integrated Ultra-High Density)
    • Amkor (Next Gen PoP, Next Gen Fine Pitch Copper Pillar)
    • Infineon/StatsChipPAC (Next Generation eWLB)
    • International Technology Roadmap for Semiconductors (Future Trends)

Students will have access to all course slides and in addition will receive a complete set of over 100 references/web links providing not only the source material but links to additional detailed information on main topics covered.

Who Should Attend?

No prior knowledge of microelectronics is required since this course is designed for the student who has little initial familiarity with Microelectronics Packaging engineering but would like to relate it to real life, everyday applications. The course uses simple terms for ease of understanding yet includes aspects of advanced packaging and industry updates and trends for senior engineers new to the field and needing a running start in packaging technology. Ideal for entry level technicians and engineers and also for people in quality assurance, sales, marketing, purchasing, safety, administration and program management.

Thomas Green


Presenter Phillip Creter has over 30 years of microelectronics packaging experience. He is currently a consultant (Creter & Associates) gaining his microelectronics packaging experience at Polymer Flip Chip Corporation, Mini-Systems, GTE and Itek Corporation. His past positions include GTE Microelectronics Center Manager (received GTE Corporate Lesley Warner Technical Achievement Award), Process Engineering Manager, Process Development Manager, Materials Engineering Manager, and Manufacturing Engineer. He has published more than a dozen technical papers, holds a U.S. patent, has given over twenty technical presentations, and has chaired numerous technical sessions for symposia. He has been teaching microelectronics courses at the college level since 1997 and since 2004, has continuously taught professional development courses at various symposia and workshops, recently adding online microelectronics webinars. He is an active certified instructor for the Department of Homeland Security currently teaching courses locally. He is a Life member of IMAPS. He was elected Fellow of the Society, National Treasurer and President of the New England Chapter (twice).



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