IMAPS PDC Webinar Series on
Electrical Test Strategies for High-Density Packages

This three-session on-line Professional Development Course (PDC) webinar will be held:
Tuesdays, April 10, 17 and 24, 2012
All webinars will be held 12:00 pm - 1:00 pm EST

Registration:
IMAPS Members: $125 per webinar; 3-course series $250
Non-members: $200 per webinar; 3-course series $500

Registration Deadline: April 9, 2012

Register On-Line

Key Words

Test, debug, bare dies, flip chip, direct-chip-attach, CSP, SIP, substrates, diagnosis, repair, modules, BGA, 3D Packaging

Program Description

This course introduces comprehensive knowledge of test solutions for advanced high-density packages by placing particular emphasis on: test and debug approaches for bare dies; testing schemes for flip-chips used in direct-chip-attach; CSP and SIP packages; testing bare substrates; and finally, test, diagnosis and repair techniques for assembled modules. Today,s miniaturization and performance requirements result in the usage of high-density advanced packaging technologies, such as system-in-package (SIP), direct-chip-attach, chip-scale packaging (CSP), and ball-grid-arrays (BGA). Due to their physical access limitation, the complexity and cost associated with their test and diagnosis are considered major issues facing their use. Some of the 3D packaging fault models and testing approaches will be discussed.

This on-line PDC is a series of 3 lectures that can be taken in total or separately depending on the experience level of the student and topics of interest. Below is a course outline for each session. Each session is scheduled for 50 minutes of lecture followed by 10 minutes of Q&A.

Session 1 of 3: Tuesday, April 10 -- 12:00-1:00 PM EASTERN

This session will cover the introduction to high density packages and their testability. We will define the levels of packaging, electronic package history through evolution, cost issues, and functions of packaging. We then move on to how to test packages. We will start with fault modeling and provide case studies of testing package at substrate and functional levels. We will conclude this session with definition of interconnects and their testing issues. We will show modeling of interconnects and some testing techniques such as capacitance, resistance and transient testing.

Session 2 of 3: Tuesday, April 17 -- 12:00-1:00 PM EASTERN

This session will cover important issues of simultaneous switching noise and IC testing techniques using built-in self-test and automatic test equipment. We will introduce design and fabrication of embedded passives.

Session 3 of 3: Tuesday, April 24 -- 12:00-1:00 PM EASTERN

This session will cover testing of embedded passives, RF IC package testing and enabling technologies in SiP, SoP, CNT and TSV. We will cover some defect modeling for 3D TSV and TSV testability. We will cover some research work in carbon nanotube based packaging.

Who Should Attend?

This course is beneficial to all design and test engineers, scientists, technical managers, design and manufacturing personnel, and production staffs in automotive, consumer, communication, computer, and aerospace industries. Although the course reviews most recent advances in electrical testing, the course does not assume prior knowledge of these issues and hence is of interest for both experts and newcomers in this area.

Presenter Dr. Bruce Kim received the B.S.E.E. degree from the University of California, Irvine in 1981, the M.S. degree in electrical engineering from the University of Arizona, and the Ph.D. degree in electrical engineering from Georgia Institute of Technology in 1996. He is an Associate Professor at The University of Alabama. He has published widely in the field of electrical testing of packages. His current research interests include RFIC testing, 3D TSVs and nano sensor packaging. Dr. Kim is a 1997 recipient of the National Science Foundation’s CAREER Award and received three Meritorious Awards from the IEEE. He is an associate editor of the IEEE Design and Test of Computers, associate editor of the IMAPS Microelectronics Journal, associate editor IEEE of Transactions of Advanced Packaging, Associate editor of Journal of Electronics Testing by Springer and BoG member of the CPMT Society of IEEE. Dr. Kim is a senior member of IEEE and IMAPS. He also serves as a technical chair of passives area for IMAPS.

Register On-Line