Members Only
Events Calendar
Online Store
Global Business Council
Industry News
IMAPS Microelectronics Foundation
Contact Us

IMAPS PDC Webinar Series on
Introduction to Microelectronics Packaging Technology

This two-session on-line Professional Development Course (PDC) webinar was held:
Wednesday, May 16 and Thursday, May 17, 2012

All webinars were held 12:00 noon - 1:00 pm EASTERN

IMAPS Members: $125 per webinar; 2-course series $200
Non-members: $200 per webinar; 2-course series $375

Download Webinar Replay

Key Words

Introduction microelectronics packaging, overview, market drivers, definitions, interconnect gap, pitch, BEOL, wafer sawing, chip attach, wire bond, package sealing, hermetic, near hermetic, LCP, solder wave, SMT, QFN, BGA, CSP, MCM, FC, Copper Pillar, MEMS, LED, Thin Wafers, Redistribution, Fan-In, Fan-Out, eWLB, underfill, 3D packaging, PoP, 3DIC, TSV, 2.5D interposers, eWLB, SoC, SiP, Future WLP, ITRS

Program Description

This up-to-date and revised introductory course provides an overview to the full spectrum of packaging from the most simple single chip package to the most advanced system level type of packaging. The approach is based upon a non-theoretical/non-academic (no mathematical equations) presentation to microelectronics packaging using simple terms. No prior knowledge of microelectronics required. Emphasis will be on visual aids and a variety of photos/figures/charts. The attendee will learn an overview of the market, basic packaging definitions, market drivers, acronyms and current terminology of materials, processes and equipment, including related technologies as applied to microelectronics and semiconductor processing. Also includes the latest updates from the International Roadmap For Semiconductors (ITRS).

Traditional assembly processes will be detailed including wafer singulation, chip attach, wire bonding, and final packaging. The general review will include components: passives, actives, chips vs. discrete SMT components and flip-chip; assembly including details of basic package types (DIP, SO, LCC, QFP, QFN, BGA, CSP, FC, 3D, and MCM). New processes/materials that enhance traditional assembly will include sintered nanosilver chip attach, fine pitch copper wire bonding, and liquid crystal polymers for near hermetic packaging.

Building upon the base of traditional assembly processing, advanced wafer level packaging will be discussed. Advanced concepts detailed include fine pitch copper pillar processes, wafer level flip chip underfill, wafer capping of MEMS, handling of thin wafers, 3D-IC TSV, 2.5D silicon and glass interposers, Fan-In/Fan-Out WLP and eWLB packaging and system packaging comparing System in Package and System on Chip. A summary of future trends of Wafer Level Packaging is provided.

Below is a course outline for each session. Each session is scheduled for 50 minutes of lecture followed by 10 minutes of Q&A.

Session 1 of 2: Wednesday, May 16 -- 12:00-1:00 PM EASTERN

The multi-billion dollar microelectronics global market reflects the most dynamic and rapidly growing industry in the world and is faced with constantly changing technology and challenges.

This lead-off session provides a brief review of the top companies and application areas along with different perspectives of the microelectronics process, establishing our background for reviewing the often-referenced Moore's Law, the classic microelectronics package, and details of the packaging process:

  • Microelectronics Market and Top Companies
  • Moore’s Law
  • Market Drivers
  • Active and Passive Chips
  • Packaging Definition, Interconnect Gap & Pitch
  • Overview/Evolution of Packaging
  • Current Mainstream of Packaging
  • Semiconductor Process (FEOL, BEOL, Levels of Packaging)
  • Back End of Line Packaging Applications
  • Traditional Assembly Process (Wafer Sawing, Chip Attach, Wire Bonding, Package Sealing)
  • Wafer Sawing (actives and passives)
  • Chip Attach (Polymer, Eutectic, SMT, Nanosilver)
  • Wire Bond (Gold, Aluminum, Copper)
  • Package Sealing (Hermetic, Near Hermetic)
  • Hierarchy of Packaging
  • Assembly Using Solder Wave and Surface Mount Technology
  • Basic Leaded Solder Wave Packages (SIP, DIP, PGA, DFP, QFP)
  • Quad Flat Pack – No Leads (QFN)
  • Basic Leaded and Leadless Surface Mount Technology (SMT) Types (SO, SOIC, DFP, QFP, QFN, Ball Grid Arrays (BGA), Chip Scale Packaging (CSP))
  • Multi-Chip-Modules (MCM)

Session 2 of 2: Thursday, May 17 -- 12:00-1:00 PM EASTERN

This session provides an overview to advanced packaging based on the definitions and basics covered in Session 1. The development of Advanced Wafer Level Packaging is proceeding in several directions to accomplish greater density using 3D stacking and lower cost by array processing at the wafer level.

  • Overview of Wafer Scale Level Packaging
  • Flip Chip Market
  • Current Industry Bumping Process
  • IBM C4NP Process
  • Injection Molding Solder Process (IMS)
  • Copper Pillar
  • Next Generation Copper Pillar
  • Traditional Underfilling
  • Wafer Level Underfilling
  • Micro-Electro-Mechanical-Systems (MEMS Market, MOEMS, Foundries, MEMS Capping)
  • Light Emitting Diodes (LED Costs, Process Flow)
  • 2.5D Interposers (Silicon, Glass)
  • Overview of 3D Packaging
  • 3D Package on Package (PoP, Thru Mold Vias)
  • 3D IC TSV Packages
  • Wafer Level Packaging
  • Handling Thin Wafers
  • Wafer Level Redistribution Fan-In/Fan-Out of Embedded Chips (eWLB Packages)
  • System in Package (SiP), System on Chip (SoC)
  • Future Trends for Wafer Level Packaging

Students will have access to all course slides and in addition will receive a complete set of over 100 references/web links providing not only the source material but links to additional detailed information on main topics covered.

Who Should Attend?

No prior knowledge of microelectronics is required since this course is designed for the student who has little initial familiarity with Microelectronics Packaging engineering but would like to relate it to real life, everyday applications. The course uses simple terms for ease of understanding yet includes aspects of advanced packaging and industry updates and trends for senior engineers new to the field and needing a running start in packaging technology. Ideal for entry level technicians and engineers and also for people in quality assurance, sales, marketing, purchasing, safety, administration and program management.

Thomas Green


Presenter Phillip Creter has over 30 years of microelectronics packaging experience. He is currently a consultant (Creter & Associates) gaining his microelectronics packaging experience at Polymer Flip Chip Corporation, Mini-Systems, GTE and Itek Corporation. His past positions include GTE Microelectronics Center Manager (received GTE Corporate Lesley Warner Technical Achievement Award), Process Engineering Manager, Process Development Manager, Materials Engineering Manager, and Manufacturing Engineer. He has published more than a dozen technical papers, holds a U.S. patent, has given over twenty technical presentations, and has chaired numerous technical sessions for symposia. He has been teaching microelectronics courses at the college level since 1997 and since 2004, has continuously taught professional development courses at various symposia and workshops, recently adding online microelectronics webinars. He is an active certified instructor for the Department of Homeland Security currently teaching courses locally. He is a Life member of IMAPS. He was elected Fellow of the Society, National Treasurer and President of the New England Chapter (twice).


© Copyright 2010 IMAPS - All Rights Reserved
IMAPS-International Microelectronics And Packaging Society and The Microelectronics Foundation
611 2nd Street, N.E., Washington, D.C. 20002
Phone: 202-548-4001