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IMAPS PDC Webinar Series on
New Developments in ADVANCED FLIP CHIP Applications

This two-session on-line Professional Development Course (PDC) webinar will be held:
Tuesday, May 7, and Thursday, May 9, 2013

All webinars will be held 12:00 noon - 1:00 pm EDT

IMAPS Members: $125 per webinar; 2-course series $200
Non-members: $200 per webinar; 2-course series $375



Key Words

28nm silicon node flip chip, bump on lead (BOL), bump on trace (BOT), copper bumps, copper pillars, coreless substrates, chip package interactions (CPI), electromigration (EM), extremely low K dielectric (ELK), electroless nickel electroless palladium immersion gold (ENEPIG), flip chip with Cu Column, bump on lead and enhanced processes (fcCuBE™), flip chip on lead frame (FCOLF), fine-pitch, flip chip, intermetallic compound (IMC), lead-free, micro-pitch, molded underfill (MUF), reliability, sapphire, thermocompression non-conductive paste (TCNCP), transient liquid phase (TLP), under bump metallization (UBM), ultra-low K dielectric (ULK), wafer level underfill (WLUF)

Program Description

This NEW webinar includes 2012 thru 1Q2013 advanced flip chip developments abstracted from conferences, technical papers, and news reports. It highlights recent advances and trends in the outlined technical topics, with enough depth to not only determine relevance but provide related references for complete information. The abstracts simplify complex concepts and use simple terms for ease of understanding; they also provide translation of the many new acronyms related to advanced flip chip technology.

The webinar includes a brief overview of the market, market drivers, single chip packaging, wafer level packaging and highlights of a recent comprehensive review of flip chip applications encompassing new advanced flip chip developments for use by engineers in design, product development, R&D and manufacturing.

New flip chip developments have been organized in the following technical areas:

Flip chip transition from solder to fine-pitch and micro-pitch copper pillars
Flip chip ElectroMigration (EM) and InterMetallic Compounds (IMC)
Flip chip reliability challenges and subsequent solutions
Low cost conversion of wire bond designs to copper column flip chip
28nm silicon node flip chip development
New flip chip interconnect technology
Flip chip wafer level underfill
Flip chip on coreless substrates (including a review of thin chip/package interactions)

Topics include a baseline of the solder paste bumping process, flip chip applications, fine pitch transition, superior advantages of copper pillar, various specific material configurations, use of SAC 305, SnCu0.7, SnAg, low temperature solder Sn57Bi and AuIn, reliability of large die, varying bump and substrate pad metallization systems, key chip package interactions, extreme and ultra-low K dielectrics, finite element modeling and Shadow-Moiré for warp studies, low cost bump on lead bonding, “damage free” processing, silver conductive paste bumps, thermocompression non-conductive paste processing, wafer level underfill for area array copper pillar flip chip with 8,000 interconnects, wafer underfill processing using non-conductive film, void-less underfill processing, non-conductive film for pre-applied wafer underfill, stress-induced thin chip package interactions, coreless substrate for ultra-thin CPU BGA packaging, and Intel® Atom™ processor flip chip on coreless substrate.

Technical innovations related to the above topics are presented with input from leading industrial/academic institutions: Altera, Amkor, Broadcom, CONNECTEC, Hitachi, IBM, IC Insights, Insights From the Leading Edge (IFTLE), IHS iSuppli, Intel, International Technology Roadmap for Semiconductors (ITRS), Micro Systems Engineering, NAMICS, Peregrine Semiconductor, Qualcomm, Taiwan Semiconductor Manufacturing Company (TSMC), Toray, Xilinx, Yole and others.

Attendees will have access to all course slides. Key slide topics include a footnote to the author, title, affiliation and source. In addition, the presenter will honor email requests for copies of selected complete references.

Below is a course outline for each session. Each is scheduled for 50 minutes of lecture followed by 10 minutes of Q&A.

Session 1 of 2: Tuesday, May 7 -- 12:00-1:00 PM EASTERN

  • Overview/market drivers
  • Single chip packaging /wafer level packaging/flip chip applications
  • Flip chip transition from solder bumps to copper pillars, fine-pitch and micro-pitch
  • ElectroMigration (EM) and InterMetallic Compounds (IMC)
  • Flip chip reliability challenges and subsequent solutions
  • Low cost conversion of wire bond designs to copper column flip chip

Session 2 of 2: Thursday, May 9 -- 12:00-1:00 PM EASTERN

  • Low cost transition of wire bond designs to flip chip
  • 28nm silicon node flip chip developments
  • New flip chip interconnect technologies
  • Flip chip wafer level underfill processing
  • Flip chip on coreless substrates (includes a review of thin chip/package interactions)

Who Should Attend?

This webinar’s specific target is the time-constrained application /product/design engineer with little to no extra time to constantly review daily news releases and/or attend major symposia and workshops to stay current with the latest technological developments in advanced flip chip processing. But, also, ideal for other engineers, scientists, and technical professionals in quality assurance, sales, marketing, purchasing, safety, administration and program management.

Thomas Green


Phillip Creter has over 30 years of microelectronics packaging experience. He is currently a consultant (Creter & Associates) gaining his microelectronics packaging experience at Polymer Flip Chip Corporation, Mini-Systems, GTE and Itek Corporation. His past positions include GTE Microelectronics Center Manager (received GTE Corporate Lesley Warner Technical Achievement Award), Process Engineering Manager, Process Development Manager, Materials Engineering Manager, and Manufacturing Engineer. He has published more than a dozen technical papers, holds a U.S. patent, has given over twenty technical presentations, and has chaired numerous technical sessions for symposia. He has been teaching microelectronics courses at the college level since 1997 and since 2004, has continuously taught professional development courses at various symposia and workshops, recently adding online microelectronics webinars. He is an active certified instructor for the Department of Homeland Security currently teaching courses locally. He is a Life member of the International Microelectronics And Packaging Society (IMAPS). He was elected Fellow of the Society, National Treasurer and President of the New England Chapter (twice).



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