Advanced System-in-Packaging (SiP) Conference
The top global virtual event for Advanced System-in-Package technologies!
Combining the 3D ASIP and IMAPS SiP events into an exciting, comprehensive program:
One event covering SiP technology developments, solutions and business trends.
A message from the Advanced SiP Event General Chair:
I want to thank all the participants and sponsors for your support for the IMAPS 2021 Advanced SiP Conference – we have received lots of positive feedback. As a reminder for those that were unable to attend on the exact days of the event, you can still view all material online through September 20 via the IMAPS portal included with your registration. If you did not register, you still can by clicking the registration link above.
- Mark Gerber, ASE Group
Here is a recap of the event:
Thorsten Meyer provided an excellent vision for where packaging is going in the automotive market. This was followed by key presentations related to heterogeneous areas and long-term roadmap considerations, including Automotive electronics, SiP for Power considerations, MEMS and Sensors Integration, Integrated Power Electronics, Modeling and Simulation and Reliability.
- Automotive Packaging - System Integration and Reliability
- HIR Overview
- Automotive Electronics
- SiP & Module
- MEMS & Sensor Integration
- Integrated Power Electronics
- Modelling & Simulation
Conference Day 1 Activity:Day 1 kicked off with 2 keynote speakers on topics related to 5G/IOT and Automotive/Power. Choon Lee (CTO of JCET) provided a vision of how 5G will pave a new phase in packaging technology. This was followed by Joy Laskar (CEO of Maja Systems) who talked about mmWave surface mount antenna technology enabling automotive solutions. Jan Vardaman held an industry expert panel session titled SiP Challenges for 5G which included multiple leading OSAT participants, as well as Fraunhofer and Cadence representatives. It was a lively discussion with some well-crafted questions by Jan. On demand, key industry invited speaker talks were available on the IMAPS portal.
KEYNOTE: 5G Paves the New Phase of the Packaging Technology
Choon Lee, JCET Group
5G is going to allow most high bandwidth users to access their mobile radio communication more efficiently. It can be possible through new or enhanced packaging technologies that include denser form factor-oriented and antenna embedded/separated structures. This talk will share the 5G related packaging technologies which enable 5G mobile products to be accommodated within allowed board space.
KEYNOTE: On the Development of mmW Surface Mount Antenna for Automotive SIP Wireless Products at the Network Edge
Joy Laskar, MAJA Systems
There has been growing interest in adoption of millimeter- wave technology for high-speed data transport to compliment current enterprise technologies, such as optical and metal-based interconnects, offering substantial advantages in band-width, reach, power consumption, and cost. It has been only recently, with the emergence of mmW radio ICs in combination with innovative antenna technology that one can envision a new class of systems and applications for low delay and high throughput connectivity. In this presentation, we focus on recent breakthroughs in Surface Mount Antenna technology enabling wireless SIP products for automotive customers at the edge of the network providing solutions for wireless data ingestion, improved connectivity and signal integrity.
Panel Session: SiP Challenges for 5G
The 5G rollout is underway for both sub 6GHz and mmWave. The design, fabrication, and test of SiPs, especially to support mmWave 5G applications, present challenges. This panel will discuss issues including design, materials, and test.
Panelists; Michael Liu, Director, JCET Group; Nozad Karim, Amkor Technology; Mark Gerber, ASE; Tanja Braun, Fraunhofer; David Vye, Cadence
Moderator: Jan Vardaman, TechSearch International
SiP Solutions for 5G/IOT
SiP Solutions for Automotive, Industrial & Power
Conference Day 2 Activity:Day 2 kicked off with 2 keynote speakers on topics related to Wearables/Medical and EDA/DSN/Modeling. Pieris Berreitter of Fitbit/Google gave a very interesting talk on The Increasing Viability of SiPs in Consumer Electronics and how it is impacting their industry and products. The second keynote Chiplets and Heterogeneous Integration Bring a New Twist to SiP was presented by Keith Felton (Mentor/Siemens) and provided a look at the design considerations for HIR. These live keynotes were followed by an interactive panel session led by Urmi Ray that was focused on Solving complex Design Challenges in HI and SIP. The discussion made it clear that HIR will bring another level of design complexity that will impact many areas.
KEYNOTE: Ever Smaller: The Increasing Viability of SiPs in Consumer Electronics
Pieris Berreitter, Fitbit/Google
The wrist of the average human has changed very little over the course of human history; meanwhile, our expectation of what's possible in a watch seems to have no bounds. As this appetite for features increases we are compelled as product developers to focus our miniaturization lens beyond the obvious targets. This talk will cover some classical SiP solutions as well as some less obvious candidates, addressing challenges unique to the consumer electronics industry. While the examples we will cover in this talk are derived from smartwatches, the fundamental elements apply to all space-constrained designs.
KEYNOTE: Chiplets and Heterogeneous Integration Bring a New Twist to SiP
Keith Felton, Siemens EDA
The semiconductor industry is facing an inflection point as higher cost, lower yield, and reticle size limitations drive the need for viable alternatives to traditional monolithic solutions, which have hit the limits of physics. This is driving an emerging trend to disaggregate what typically would be implemented as an SoC into solid, fabricated IP blocks, otherwise known as chiplets. These chiplets typically include just a couple of functions implementated at the optimal process node, when combined with other chiplets, memory and often a custom ASIC results in a multi-die heterogeneous integrated implementation that typically utilizes a high-performance substrate ushering in a new generation of system-in-package and with it a new set of design challenges that we will explore.
Panel: Solving Complex Design Challenges in HI and SiP
The emerging trend of complex HI packages, including 2.5D/3D, RFFEM exacerbates design and validation challenges. This panel will address solution strategies from R&D to execution.
Panelists: Javi DeLaCruz, ARM, George Harris, Amkor Technology, Madhavan Swaminathan, Georgia Tech, and Keith Felton, Siemens EDA
Moderator: Urmi Ray, Consultant
SiP market and technology trends for wearables applications
Santosh Kumar, Yole
Bio-sensing and its Integration in Wearables
Henry Lin, ASE Group
Applying Silicon Photonics to Health Sensor Technology
Dave McCann, Rockley Photonics
Strategies for 2.xD and 3D Integration
Javi DeLaCruz, ARM
Design Flow Challenges for Silicon-centric
John Park, Cadence
Ansys: Solving the Unsolvable
Kevin Quillen, ANSYS
Conference Day 3 Activity:
The final day featured 2 keynote speakers that kicked off tracks on High Performance Computing and Silicon Photonics and Advanced Test and Yield Enhancement. Jorge Hurtarte (Teradyne) focused on mmWave and 6G test considerations and provided a broad overview of the spectrum challenges that will need to be addressed, including mmWave, as well as platforms and test methods to cover both 5G and what to expect for 6G. Mark Wade (President and CTO of Ayar Lab) shared insights on the new HPC speed requirements and methods on how Ayar Labs is getting there with the enablement of advanced silicon and silicon photonics packaging. Both presentations were outstanding and a must see if you missed. The final panel session led by Eelco Bergman featured another lively discussion on HPC and Chiplet Integration. Panelists from Google, Facebook, Teradyne and Ansys rounded out this discussion and touched on a number of key industry challenges.
KEYNOTE: From 5G mmWave to 6G THz: What‘s Next in RF Test Challenges?
Jeorge Hurtarte, Teradyne
As each G in mobile networks generations takes about eight years to follow the previous one, we‘re only about five years from facing new 6G THz test challenges. And given that 5G mobile networks are just ramping up with high volume millimeter wave devices, is it too early to start worrying about 6G test challenges? This presentation starts with an overview of the possible 6G use cases that make THz a requirement as we enter into the second half of this decade and then follows with a preview of the test challenges that can be expected for 6G beyond the current 5G millimeter wave test challenges.
KEYNOTE: optical I/O Chiplets for Next-Generation Heterogeneous Computing
Mark Wade, Ayar Labs
Electrical communications technologies are facing challenges in scaling bandwidth while achieving compelling energy efficiency, bandwidth density, latency, and reach. While digital processing performance continues to scale in how much compute can be achieved per unit area of silicon, the ability to fuel processing cores with bandwidth has become a major limiting factor for many high-value workloads, such as machine learning. A new I/O technology is needed that can match the performance requirements needed for computing fabrics and have a viable path to scale to high-volumes. In this talk, we present progress towards a new generation of densely integrated optical I/O technologies that address the bandwidth density, energy efficiency, and scalability requirements for next-generation computing fabrics and demonstrate a new overall chip-to-chip I/O architecture based on this technology.
Panel Session on:
Chiplet Integration for HPC Applications - Enabling Mass Adoption
The industry shift to hetero/homogeneously integrated based chip design solutions has started and initial products have been introduced by several leading player who have the ability to vertically control the device and interface designs for all parts of the integrated solution. The topic we want to address is what are the challenges and opportunities that will enable broad based adoption of this new paradigm in the design of advanced server and network processors and SoC‘.
Panelists: Jeorge Hurtarte, Teradyne; Ravi Agarwal, Facebook; Kevin Quillen, ANSYS;
Amit Marathe, Google
Moderator: Eelco Bergman, ASE Group
SiP Test & Yield Enablement
Packaging Challenges and Opportunities for mmWave Communications
Dr. Madhavan Swaminathan, Georgia Tech
Ravi Agarwal, Facebook
Chris Scanlan, Besi
SiP Test Solution for 5G/IoT
Vineet Pancholi, Amkor Technology
Minimizing deleterious radiation effects in sensitive CMOS devices while maintaining 100% coverage strategies for X-ray defect inspection in double-sided SiP manufacturing
Francisco Machuca, SVXR
Overview of Warpage and Void Simulations for System in Package (SiP)
Eric Ouyang, JCET
Once again, we thank those who were able to join and encourage others to see all the on-demand content in the IMAPS portal. I look forward to seeing you again at next year‘s SiP Conference in June at the DoubleTree in Sonoma, CA.
Join us in-person in Sonoma for SiP 2022!
June 21-23, 2022
DoubleTree by Hilton Sonoma - Wine Country
Details soon at: www.advancedsip.org
Invited Speakers Only | Panel Sessions | PDCs
Sponsorships & Exhibits Opening Soon!